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[SI-LIST] Re: Differential Pair Characteristic Impedance Tradeoffs
- From: Dennis Han <Dennis.Han@xxxxxxxxxxx>
- To: Julia Nekrylova <fialka113@xxxxxxxxx>
- Date: Fri, 07 Oct 2005 07:30:48 -0500
No, but that is how the PCB fabricator sends its data. My guess is they
send averages of the material types, a prepreg in this case. The other
prepregs in the stack-up were 3.85 and the cores were 4.10. I'll take
averages since these are real. The averages are not in the middle of the
material manufacturers' ranges for Er by the way. I don't know how long
thisfabricator has been collecting data to compute the averages, but I would
bet it started in the 90's. I know of at least one fabricator that started
published averages in the early 90's.
Dennis
Julia Nekrylova wrote: Dennis, Was it really "Er of 4.03" in your design?
Hundredths in the dielectric constant value would not make sense knowing the
typical manufacturing tolerances in FR4. Julia
Dennis Han <Dennis.Han@xxxxxxxxxxx>[1] wrote: It doesn't make sense to have
asingle-ended constraint on differential
lines. A common-mode constraint makes more sense. I think your
single-ended constraint, meaning a single line that is not part of a
differential pair, is 60 ohms. Your differential constraints, meaning
two lines that are purposely coupled, are 90 ohms (and probably 30 ohms
common-mode if this if for USB) and 100 ohms. Then you can solve the
problem.
Er for FR4 is usually around 3.7 to 4.2, depending on the cores and
prepregs that are used. Since this is microstrip, take into account the
solder mask, which has an Er of approximately 3.75 and a thickness of
around 0.8 mils.
I recently designed microstrip 90-ohm differential (twice Zodd) and
30-ohm common-mode (half Zeven) microstrip with a 3 mill dielectric at
Er of 4.03 plus the solder mask. Line widths were 4.0 mils and space
was 6.5 mils. The finished copper thickness was 2.0 mils.
Dennis
melvin bowman wrote:
>I find, in attempting to determine trace and space widths for multiple
>differential pairs with different impedance requirements on a single PCB
>layer, it can be impossible to find a perfect solution while staying
>within acceptable manufacturing constraints.
>I.e. Given the following.
>
>Impedance Requirements
>Single-ended (default) trace is desired to have a Zo a of 60-ohms.
>Diff. Pair #1 characteristic impedance = 60-ohms single-ended and
>100-ohms differential.
>Diff. Pair #2 characteristic impedance = 60-ohms single-ended and
>90-ohms differential.
>All impedances specified with a tolerance of +/-10%.
>
>Manufacturing Constraints
>Single-ended (default) trace with = 5 mils.
>Minimum trace width = 5 mils.
>Minimum space width = 5 mils.
>Trace thickness (t) = 0.7 mils or 1.4 mils (1/2 oz. or 1 oz. copper)
>Dielectric thickness (h) = 4 - 5 mils (microstrip).
>Effective dielectric constant (Er) = attainable values with FR4 (3.4 -
>4.8 ???) What is the reasonable range?
>
>From the constraints, above, we can see that both diff. pairs #1 and #2
>will have a trace width of 5 mils, as they have the same single-ended
>characteristic impedance as that of the default single-ended 5 mil trace.
>
>Given this information we can determine a dielectric thickness (t) and
>effective dielectric constant (Er) to meet the requirements for diff.
>pair #1 while staying within the bounds of our manufacturing
>constraints. However, at this point we have the diff. pair #2
>requirements to contend with. As diff. pairs # 1 and #2 are both on the
>same layer and have the same single-ended characteristic impedance they
>must both have the same trace width (5 mils). This leaves us with only
>one parameter to adjust to get a 90-ohm differential impedance for diff.
>pair #2 while maintaining a 100-ohm differential impedance for diff.
>pair #1. When we attempt to set a differential pair spacing to attain a
>90-ohm differential impedance for diff. pair #2 we find that we can't
>get them close enough together to accomplish this without seriously
>violating our minimum space width constraint of 5 mils.
>
>Our only solution appears to be to compromise on the characteristic
>impedances of our various traces, both single-ended and differential.
>When we do this we begin to eat away at the +/-10% tolerance that was
>intended to be a manufacturing tolerance, not a calculation tolerance.
>
>If we make this compromise we come up with numbers such as the following
>scenario.
>
>Single-ended (default) trace = 5 mils and 60-ohms.
>Diff. Pair #1 = 5 mils and 60/101-ohms with a 5 mil spacing..
>Diff. Pair #2 = 5.7 mils and 56/94-ohms with a 5 mil spacing.
>This is accomplished with a trace thickness (t) of 1 mil, a dielectric
>thickness (h) of 4.3 mils and an Er of 4.2.
>(Note that I used a 1 mil thickness rather than 0.7 or 1.4. This was
>just to split the difference for ease of analysis and has a small impact
>on the overall result. Likewise, different impedance calculators may
>give different numbers but the trend should provide similar results)
>
>Assuming that no one can tell me how to get the calculations to work out
>exactly to the requirements without violating the manufacturing
>constraints, this leads to my actual question(s).
>
>1) How important is the single-ended impedance of the traces of a
>differential pair and what is the impact of a deviation of 5% - 10%?
>
>2) Is the best compromise to target the desired single-ended impedance
>for the benefit of the non-differential default traces and adjust the
>width and spacing of the differential pairs to give the desired
>differential impedances while violating their single-ended impedance
>specifications?
>
>3) Is it better to compromise all impedances, default single-ended as
>well as diff. pair single-ended and differential impedances and just try
>to find a tradeoff that keeps them all relatively close to their desired
>values, if possible?
>
>4) If the answer to question #1 hasn't already answered this question,
>what is the importance of the single-ended impedance of a differential
>pair, as long as it's balanced (both traces have the same single-ended
>impedance).
>
>
>
>
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