FreeLists / si-list / [SI-LIST] Re: Chip level IBIS Modeling.

[Ray Anderson <reanderson@xxxxxxxxxxxxx>]

Siva-

I don't believe that  learning about IBIS model generation in detail as 
you have requested is one of those things that is going to realistically 
happen on a mailing list such as si-list and ibis-list.

There is a lot of info on the web about IBIS. Try looking over the 
following sites as a starter. Learn what you can there from the 
documents and papers you find and then follow the links on those pages 
for further info:

*ANSI/EIA-656-A IBIS Home Page: *_*http://www.eigroup.org/ibis/ibis.htm*_
*IBIS (I/O Buffer Information Specification) page:** 
*_*http://www.eda.org/pub/ibis*_
*IBIS Utilities page from Teraspeed:** 
*_*http://www.teraspeed.com/ibis_resources.html#utilities*_
Lynne Green's Green Streak Programs (IBIS and SI on-site training) [ 
_www.greenstreakprograms.com_ <http://www.greenstreakprograms.com> ]


Some of the above mentioned web resources  have links to online 
seminars, published papers and other useful info.

Perhaps enlisting the services of a consultant who specializes in IBIS 
modeling could solve your immediate need for models and at the same time 
contribute to your knowledge of the subject.


Good Luck,

Ray Anderson



palaniappan.sivakumar@xxxxxxxxx wrote:

>Hi Experts,
>
>It would be of great help if any one could let me know how the Chip level IBIS 
>modelling is done.We would like to understand the chip level IBIS models and 
>its generation in detail.
>
>As we know chip level IBIS modelling includes number of Pins and its pkg 
>parameters, how do we include pad pins and pkg parasitics?
>
>Can I specify more than one pkg models available in more than one .pkg file in 
>to an IBIS model? if so how?
>
>Can any one know where can I get some guidelines for Chip level IBIS model 
>creation.?
>
>Any guidance would be appreciated.
>
>Thanks in Advance.
>
>Regards,
>Sivakumar
>
>  
>

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