FreeLists / si-list / [SI-LIST] Re: negative propagation delay

[Perry Qu <perry.qu@xxxxxxxxxxx>]

Thanks, Ricky. I think Tco+Tflight could vary significantly depending on
termination, topology, etc. for a daisy-chained bus, due to reflection.
That's the whole purpose to calculate delay through simulation.

As a few people pointed out to me offline, negative delay should be ok as it
reflected the situation that Tco for my real load should be smaller since my
real load is smaller. I should have more margin for setup. I guess the only
reason I need to watch out negative delay is for hold time margin, since if
I plugged in a negative delay for Hold time margin calculation, I may end up
with negative margin.

Thanks

Perry

"Lai, Ricky (Eng Hou)" wrote:

> The basic timing equation for:
> Setup Margin = clk_period - Tco - Tflight - Tsu
> With a large reference load, the Tco will be large, the Tflight will be
> small or in some case, may be even negative.
> With a small reference load, the Tco will be small, but in this case,
> the Tflight will be large.
>
> In both cases, Tco + Tflight will equal the same value.  Therefore, it
> does not matter whether you are using a large reference load or not.
>
> In reality, Tco can be separate into 2 numbers: Tcq and Tqo.  Tcq is the
> prop delay of the internal logic to the last q output stage.  Tqo is the
> buffer delay into a reference test load.  If you are using your internal
> ASIC, then your logic folks should be able to provide you with the Tcq
> number.
>
> Ricky
>
> -----Original Message-----
> From: Perry Qu [mailto:perry.qu@xxxxxxxxxxx]
> Sent: Thursday, October 02, 2003 2:03 PM
> To: si-list
> Subject: [SI-LIST] negative propagation delay
>
> Hi,
>
> I'm using ICX for SI/timing analysis. One thing I noticed, if a driver
> IBIS specified a large reference load (e.g., 50pF for uP), I will always
> end up with a negative propagation delay since my actual loading is much
> smaller compared with reference load.
>
> Would like to understand how I should correct the number to reflect my
> actual loading for timing analysis. I would think we can get the
> internal logic delay of driver through: (Tco - time_to_Vmeas@reference
> load); But then, how shall I add buffer delay for a real load and
> propagation delay for a real load--taking into account all the
> reflection effect (e.g., a daisy-chained bi-directional data bus).
>
> Thanks
>
> Perry
>
> --
> Perry Qu
>
> Design & Qualification       |      600 March Road
> Alcatel Canada               |      Ottawa, ON K2K 2E6, Canada
>
> DID: (613) 7846720           |      FAX: (613) 5993642
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--
Perry Qu

Design & Qualification       |      600 March Road
Alcatel Canada               |      Ottawa, ON K2K 2E6, Canada

DID: (613) 7846720           |      FAX: (613) 5993642


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