FreeLists / si-list / [SI-LIST] Re: How to measure package impedance or characteristic for a chip?

[Ullrich Pfeiffer <ullrich@xxxxxxxxxx>]

Dear John Lin,

you may want to check a conference contribution at the IEEE 11th 
Topical Meeting on Electrical Performance of Electronic Packaging. 
(October 21-23, 2002, in Monterey, California). I will give a 
presentation about a Non-Destructive S-Parameter Measurement of a 
Hermetically Encapsulated Package. The method is based on S-parameter 
measurements using a plain VNA in conjunction with a 
Port-Reduction-Method (PRM). 

Title:
"Non-Destructive S-Parameter Measurement of a Hermetically 
Encapsulated Package with Comparison to High-Frequency Simulation"
(Session X, Measurements on Wednesday, October 23rd from 8:30 AM - 
9:50 AM)

Ullrich

On Thursday 03 October 2002 09:23 pm, you wrote:
> Dear all SI gurus,
> Can somebody help to provide me a way to measure chip package
> impedance without separating die and package? Can a TDR be used to
> do so?  Or what instruments, such as VNA,  to do so? Do I need to
> make a fixture on PCB to measure it?
>
> Thank you for your helps in advance :-)
>
> John Lin
>
> Quanta Computer Inc.,Taiwan, R.O.C.
> Email: John@xxxxxxxxxxxx
> Tel: 886+3+3272345 ext. 5183
>
>
>
>
>
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