Date Index for si-list, 10-2002

[si-list] || [10-2002 Date Index] [10-2002 Thread Index]

[SI-LIST] Re: 2.5Gbit connectors and cables - Gil Gafni
[SI-LIST] Re: A SPICE TO IBIS CONVERSION PROBLEM - Jineshwari B - CTD, Chennai.
[SI-LIST] BC Fabricator in Hong Kong - Peter Baxter
[SI-LIST] Re: 2.5Gbit connectors and cables - Shimshon Jacobi
[SI-LIST] Re: A SPICE TO IBIS CONVERSION PROBLEM - Mike LaBonte
[SI-LIST] Re: 2.5Gbit connectors and cables - Bao Lenguyen
[SI-LIST] Re: 2.5Gbit connectors and cables - Gupta, Deepali
[SI-LIST] Re: 2.5Gbit connectors and cables - Bob Patel
[SI-LIST] Re: A SPICE TO IBIS CONVERSION PROBLEM - Ingraham, Andrew
[SI-LIST] Re: Planar DDR and LVTTL I/O - jim freeman
[SI-LIST] Re: SI job opportunity: Technical Marketing Engineer - Dima Smolyansky
[SI-LIST] SI job opportunity: Technical Marketing Engineer - Dima Smolyansky
[SI-LIST] Re: 2.5Gbit connectors and cables - john lipsius
[SI-LIST] Re: Planar DDR and LVTTL I/O - Ravinder Ajmani
[SI-LIST] Re: Planar DDR and LVTTL I/O - Mike Brown
[SI-LIST] Jitter Characterization on a Tester? - Jay Shenoy
[SI-LIST] Differential microstrip with coplanar ground traces ... unexpected results - Bob Welte
[SI-LIST] Re: 2.5Gbit connectors and cables - Fabrizio
[SI-LIST] Re: Jitter Characterization on a Tester? - Ingraham, Andrew
[SI-LIST] Re: Differential microstrip with coplanar ground traces... unexpected results - Scott McMorrow
[SI-LIST] Re: Differential microstrip with coplanar ground traces ... unexpected results - Ed Sayre III
[SI-LIST] Re: Differential microstrip with coplanar ground traces ... une... - MikonCons
[SI-LIST] Re: Differential microstrip with coplanar ground traces - MikonCons
[SI-LIST] Re: Differential microstrip with coplanar ground traces - Rohit Mittal
[SI-LIST] Re: Differential microstrip with coplanar ground traces - MikonCons
[SI-LIST] Re: Differential microstrip with coplanar ground traces ... unexpected results - Loyer, Jeff
[SI-LIST] Re: Differential microstrip with coplanar ground traces ... unexpec... - MikonCons
[SI-LIST] RMCEMC October Meeting - Charles Grasso
[SI-LIST] Hyper Transport Probe - Raja
[SI-LIST] Re: Differential microstrip with coplanar ground traces ... unexpectedresults - Bob Welte
[SI-LIST] Re: Hyper Transport Probe - evillaf
[SI-LIST] Re: A SPICE TO IBIS CONVERSION PROBLEM - Abhijit Mahajan
[SI-LIST] Receiver/transmitter offset-sensitivity - Gupta, Naveen
[SI-LIST] dc blocking caps in 10G lines - Rohit Mittal
[SI-LIST] FW: Innoveda User's Groups - Chuck Reynolds
[SI-LIST] Resume for Design/Applications Engineer - Uzma Khan
[SI-LIST] How to measure package impedance or characteristic for a chip? - =?big5?b?Sm9obiBMaW4gKKpMtMK31yk=?=
[SI-LIST] PWB coupling to system enclosures - Douglas C. Smith
[SI-LIST] test -- please ignore this mail - flin
[SI-LIST] Eye pattern with HSPICE - Gil Gafni
[SI-LIST] Re: Eye pattern with HSPICE - Clewell, Craig
[SI-LIST] Hyper Transport Probe Details - Raja
[SI-LIST] Re: How to measure package impedance or characteristic for a chip? - Ullrich Pfeiffer
[SI-LIST] Unconnected pins in a connector carrying differential signals - Jineshwari Baratharajan
[SI-LIST] Creating IBIS models for a fee? - Mike Cantwell
[SI-LIST] Re: Unconnected pins in a connector carrying differential signals - Ingraham, Andrew
[SI-LIST] Re: Unconnected pins in a connector carrying differentialsignals - Lieby David
[SI-LIST] Re: Creating IBIS models for a fee? - Douglas Burns
[SI-LIST] How to??? - Kevin Buchanan
[SI-LIST] Re: Creating IBIS models for a fee? - Tom Dagostino
[SI-LIST] Re: Creating IBIS models for a fee? - Scott McMorrow
[SI-LIST] Re: Unconnected pins in a connector carrying differential signals - DAmbrosia, John F
[SI-LIST] Re: Differential microstrip with coplanar ground traces ... unexpected results - Michael Smith
[SI-LIST] Re: Differential microstrip with coplanar ground traces... unexpected results - Scott McMorrow
[SI-LIST] Class on Gigabit design at PCB East - Scott McMorrow
[SI-LIST] Re: Differential pair impedance - Pat Diao
[SI-LIST] Why 220ohms at driver end in PECL Terminations - Jineshwari B - CTD, Chennai.
[SI-LIST] Recall: Why 220ohms at driver end in PECL Terminations - Jineshwari B - CTD, Chennai.
[SI-LIST] Why 220ohms at driver end in PECL Terminations - Jineshwari B - CTD, Chennai.
[SI-LIST] Re: Why 220ohms at driver end in PECL Terminations - Stuart Brorson
[SI-LIST] Re: How to measure package impedance or characteristic for a chip? - Isaac Kantorovich
[SI-LIST] Re: Differential pair impedance - Abe Riazi
[SI-LIST] Re: Why 220ohms at driver end in PECL Terminations - Ingraham, Andrew
[SI-LIST] RE How to - Kevin Buchanan
[SI-LIST] Interface of Microphone with Codec - Adeel Malik
[SI-LIST] AC Waveform question - Doug Brooks
[SI-LIST] Re: AC Waveform question - Zabinski, Patrick J.
[SI-LIST] Re: AC Waveform question - Stuart Brorson
[SI-LIST] AC Waveform question, clarification - Doug Brooks
[SI-LIST] Re: AC Waveform question - Jackson, T L
[SI-LIST] Re: AC Waveform question - Dunbar, Tony
[SI-LIST] Re: AC Waveform question - Jackson, T L
[SI-LIST] Re: Why 220ohms at driver end in PECL Terminations - Suresh Sivasubramaniam
[SI-LIST] Re: AC Waveform question - Ed Miguel
[SI-LIST] Re: AC Waveform question - Ingraham, Andrew
[SI-LIST] Re: AC Waveform question - Doug McKean
[SI-LIST] Re: AC Waveform question - Tom Dagostino
[SI-LIST] Re: How to measure package impedance or characteristic for a chip? - Quyen Vu
[SI-LIST] test - Adeel Malik
[SI-LIST] Some Querries regarding Xtalk in traces - Anshuli Goel
[SI-LIST] Re: AC Waveform question - Jochen Feldhaar
[SI-LIST] complex numbers - Alicia Corrales Chanca
[SI-LIST] Hi all - Sathish
[SI-LIST] Re: Differential microstrip with coplanar ground traces - Rohit Mittal
[SI-LIST] Re: Differential microstrip with coplanar ground traces - MikonCons
[SI-LIST] analog / mixed signal simulation - Roger_Wu
[SI-LIST] Re: Serpentine Traces - Jack W.C. Lin
[SI-LIST] Re: How to measure package impedance or characteristic for a chip? - Isaac Kantorovich
[SI-LIST] Re: Serpentine Traces - Jack W.C. Lin
[SI-LIST] how to reduce hspice run-time? - Yoni Tzafrir
[SI-LIST] Package Parasitics of 168-PIN DIMM Socket - Adeel Malik
[SI-LIST] 2D transmission line theory - Zhangkun
[SI-LIST] Antw: Package Parasitics of 168-PIN DIMM Socket - Robert Nowak
[SI-LIST] Re: how to reduce hspice run-time? - Michael J. Degerstrom
[SI-LIST] Re: how to reduce hspice run-time? - Clewell, Craig
[SI-LIST] Re: 2D transmission line theory - Jeff Jones
[SI-LIST] Re: Antw: Package Parasitics of 168-PIN DIMM Socket - Clewell, Craig
[SI-LIST] Re: Serpentine Traces - Dunbar, Tony
[SI-LIST] 20H Rule theoretically investigated with simulation. - Doug McKean
[SI-LIST] "Line Errors" in Gigabit Ethernet - Gupta, Naveen
[SI-LIST] Re: 20H Rule theoretically investigated with simulation. - Doug McKean
[SI-LIST] Re: Package Parasitics of 168-PIN DIMM Socket - Gregory R Edlund
[SI-LIST] Re: 20H Rule theoretically investigated with simulation. - Ritchey Lee
[SI-LIST] Re: SPICE on the cheap? - Stuart Brorson
[SI-LIST] Re: SPICE on the cheap? - Clewell, Craig
[SI-LIST] Re: SPICE on the cheap? - Ray Anderson
[SI-LIST] Other mailing lists for system-level SI issues? - Steven Kan
[SI-LIST] Re: SPICE on the cheap? - Ed Miguel
[SI-LIST] Re: Other mailing lists for system-level SI issues? - Ray Anderson
[SI-LIST] Re: 20H Rule theoretically investigated with simulation. - pwelling
[SI-LIST] Re: SPICE on the cheap? - Clewell, Craig
[SI-LIST] Re: SPICE on the cheap? - Jian X. Zheng
[SI-LIST] Re: Other mailing lists for system-level SI issues? - Raja Patil
[SI-LIST] Re: Serpentine Traces - Jack W.C. Lin
[SI-LIST] Re: Serpentine Traces - Dunbar, Tony
[SI-LIST] Recommendation for edge launched SMA connector for 0.093" board. - Vipul Badoni
[SI-LIST] Why SSTL_2 does not need 1_25V Pull Up in AGP card? - Jack W.C. Lin
[SI-LIST] Re: Serpentine Traces - Peng.Smith
[SI-LIST] Re: Why SSTL_2 does not need 1_25V Pull Up in AGP card? - chris . mcgrath
[SI-LIST] Opportunity query - SDSIGUY
[SI-LIST] AC Coupling Capacitors for LVPECL Signals - Jineshwari B - CTD, Chennai.
[SI-LIST] The model of Cat 5 UTP cable - Nekrylova, Julia
[SI-LIST] Re: The model of Cat 5 UTP cable - Jerry Martinson
[SI-LIST] Re: AC Coupling Capacitors for LVPECL Signals - Rohit Mittal
[SI-LIST] Re: The model of Cat 5 UTP cable - Patrick O'Shea
[SI-LIST] Re: AC Waveform question - Ingo Kupper
[SI-LIST] Re: SPICE on the cheap? - Al Davis
[SI-LIST] Re: SPICE on the cheap - Jay Shenoy
[SI-LIST] Re: The model of Cat 5 UTP cable - Raymond . Leung
[SI-LIST] Re: SPICE on the cheap - Bhupendra Kapoor
[SI-LIST] Re: AC Coupling Capacitors for LVPECL Signals - Steven Kan
[SI-LIST] Re: Differential microstrip with coplanar ground traces ... unexpectedresults - Lewandowski, Bob
[SI-LIST] Re: SPICE on the cheap - Jay Shenoy
[SI-LIST] Re: Why SSTL_2 does not need 1_25V Pull Up in AGP card ? - Mike Brown
[SI-LIST] Re: SPICE on the cheap - Al Davis
[SI-LIST] Re: Why SSTL_2 does not need 1_25V Pull Up in AGPcard ? - Scott McMorrow
[SI-LIST] Re: 2D transmission line theory - Larry Smith
[SI-LIST] Re: Differential microstrip with coplanar ground traces ... unexpectedresults - Bob Welte
[SI-LIST] Impedance calculation of asymmetric coupled lines? - D G
[SI-LIST] New Senior Signal Integrity Positions available in AustinTX.... - Michael_Greim
[SI-LIST] Re: Impedance calculation of asymmetric coupled lines? - D G
[SI-LIST] HSpice Models in SPECCTRAQuest - Andreas Grübl
[SI-LIST] Re: SPICE on the cheap - Yu Liu
[SI-LIST] Re: HSpice Models in SPECCTRAQuest - Ray Anderson
[SI-LIST] Re: SPICE on the cheap - Clewell, Craig
[SI-LIST] Re: SPICE on the cheap - Muranyi, Arpad
[SI-LIST] Re: SPICE on the cheap - Scott McMorrow
[SI-LIST] Re: HSpice Models in SPECCTRAQuest - Juergen Flamm
[SI-LIST] CosmoScope - Khalid Ansari
[SI-LIST] Re: HSpice Models in SPECCTRAQuest - Todd Westerhoff
[SI-LIST] Reenviar: RESUME - mmirfan
[SI-LIST] Reenviar: RESUME - mmirfan
[SI-LIST] Re: HSpice Models in SPECCTRAQuest - Ray Anderson
[SI-LIST] Re: HSpice Models in SPECCTRAQuest - Mohammad Ali
[SI-LIST] Re: HSpice Models in SPECCTRAQuest - Donald Telian
[SI-LIST] RESUME - mmirfan
[SI-LIST] Suggestions on the length of lines - Ravi S. Urs
[SI-LIST] What must be considered for simulation of 5Gbit differential signals on FR-4 PCB? - =?big5?b?Sm9obiBMaW4gKKpMtMK31yk=?=
[SI-LIST] Re: Suggestions on the length of lines - Bill Hargin
[SI-LIST] Re: New Senior Signal Integrity Positions available in AustinTX. ...and more!! - Michael_Greim
[SI-LIST] Re: AC Coupling Capacitors for LVPECL Signals - Ingraham, Andrew
[SI-LIST] running scripts with CosmoScope & Hspice - Yoni Tzafrir
[SI-LIST] JOB OPPORTUNITIES THAT DO NOT EXIST (VAPOR JOBS) - simsoc radt
[SI-LIST] Sigrity Extends Offer for Free Training of SI Tools - Teo Yatman
(no subject) - mmirfan
[SI-LIST] Re: running scripts with CosmoScope & Hspice - Tracy Barclay
[SI-LIST] Question Regarding Some IBIS Parameters - Timothy Coyle
[SI-LIST] Re: Suggestions on the length of lines - houfei chen
[SI-LIST] Search for a part - Adeel Malik
[SI-LIST] Constraints on DQ/DQS and CK/CK# in DDR - Jack W.C. Lin
[SI-LIST] Re: Constraints on DQ/DQS and CK/CK# in DDR - John Phillips
[SI-LIST] Re: Constraints on DQ/DQS and CK/CK# in DDR - Jack W.C. Lin
[SI-LIST] AW: Question Regarding Some IBIS Parameters - Lenski Eckhard
[SI-LIST] Re: AW: Question Regarding Some IBIS Parameters - Timothy Coyle
[SI-LIST] Re: Constraints on DQ/DQS and CK/CK# in DDR - Eric Deys
[SI-LIST] Pick & Place Machines operation - Adeel Malik
[SI-LIST] How to Verify C_comp - Timothy Coyle
[SI-LIST] Re: Pick & Place Machines operation - Matthew Humphreys
[SI-LIST] Re: SPICE on the cheap - Mellberg Hans
[SI-LIST] Re: SPICE on the cheap - Ray Anderson
[SI-LIST] Beyond Rail Operation in IBIS - Abhijit Mahajan
[SI-LIST] Re: Constraints on DQ/DQS and CK/CK# in DDR - Vinu Arumugham
[SI-LIST] Re: Beyond Rail Operation in IBIS - Volk, Andrew M
[SI-LIST] Senior SI Positions with TI in Austin - Brian Young
[SI-LIST] Re: Beyond Rail Operation in IBIS - Robert Haller
[SI-LIST] Re: Beyond Rail Operation in IBIS - Abhijit Mahajan
[SI-LIST] Re: Beyond Rail Operation in IBIS - Robert Haller
[SI-LIST] Re: Impedance calculation of asymmetric coupled lin es? - houfei chen
[SI-LIST] Re: Impedance calculation of asymmetric coupled lines? - houfei chen
[SI-LIST] Re: Constraints on DQ/DQS and CK/CK# in DDR - Robert Sefton
[SI-LIST] Re: Impedance calculation of asymmetric coupled lines? - D G
[SI-LIST] Re: Constraints on DQ/DQS and CK/CK# in DDR - Tadashi Arai
[SI-LIST] Re: Constraints on DQ/DQS and CK/CK# in DDR - Moran, Brian P
[SI-LIST] Re: Constraints on DQ/DQS and CK/CK# in DDR - Jack W.C. Lin
[SI-LIST] Re: How to Verify C_comp - Gregory R Edlund
[SI-LIST] Re: Constraints on DQ/DQS and CK/CK# in DDR - James_R_Jones
[SI-LIST] Re: Search for a part - John Coupland
[SI-LIST] Low inductance chip capacitor(LICC) - Perry Qu
[SI-LIST] Low inductance chip capacitor(LICC) - Steve Horne
[SI-LIST] Re: Low inductance chip capacitor(LICC) - Ritchey Lee
[SI-LIST] Re: Pick & Place Machines operation - Erhan Kaya
[SI-LIST] Re: Low inductance chip capacitor(LICC) - Perry Qu
[SI-LIST] Re: Low inductance chip capacitor(LICC) - Larry Smith
[SI-LIST] Re: Low inductance chip capacitor(LICC) - Michael Khusid
[SI-LIST] Re: Low inductance chip capacitor(LICC) - Juergen Flamm
[SI-LIST] Re: Low inductance chip capacitor(LICC) - Krina Kothari
[SI-LIST] Re: Impedance calculation of asymmetric coupled lines? - john lipsius
[SI-LIST] Re: Impedance calculation of asymmetric coupled lin es? - john lipsius
[SI-LIST] Differential trace route question - Doug Brooks
[SI-LIST] Re: Low inductance chip capacitor(LICC), IDC - Mark Alexander
[SI-LIST] Re: Impedance calculation of asymmetric coupled lines? - john lipsius
[SI-LIST] Re: Low inductance chip capacitor(LICC), IDC - Istvan Novak - Board Design Technology
[SI-LIST] Re: Differential trace route question - Lewandowski, Bob
[SI-LIST] Interfacing Single ended PECL signal to differential PECL pair - Nagammai Periya Karuppan. - CTD, Chennai.
[SI-LIST] Re: Differential trace route question - James_R_Jones
[SI-LIST] Re: Differential trace route question - Paul Levin
[SI-LIST] Re: Differential trace route question - christopher . heard
[SI-LIST] Re: Low inductance chip capacitor(LICC), IDC - Michael Khusid
[SI-LIST] Re: Search for a part - Adeel Malik
[SI-LIST] Re: Interfacing Single ended PECL signal to differential PECL pair - Bill Dempsey
[SI-LIST] Re: Beyond Rail Operation in IBIS - Ingraham, Andrew
[SI-LIST] Re: Low inductance chip capacitor(LICC), IDC - Perry Qu
[SI-LIST] Re: Beyond Rail Operation in IBIS - Tom Dagostino
[SI-LIST] AC Coupling and Differential Pair's Termination - ggafni
[SI-LIST] SMA replacement - Kikito Vertiginopulos
[SI-LIST] Re: Beyond Rail Operation in IBIS - Al Davis
[SI-LIST] Re: SMA replacement - Mellberg Hans
[SI-LIST] Re: SMA replacement - Ray Anderson
[SI-LIST] Re: AC Coupling and Differential Pair's Termination - James_R_Jones
[SI-LIST] Re: SMA replacement - Tom Dagostino
[SI-LIST] W-element - ttsp
[SI-LIST] Re: W-element - Beal, Weston
[SI-LIST] Re: W-element - Ray Anderson
[SI-LIST] Re: W-element - Volk, Andrew M
[SI-LIST] Re: SMA replacement - Randol Mark-ryvw50
[SI-LIST] Re: AC Coupling and Differential Pair's Termination - Loyer, Jeff
[SI-LIST] Re: Differential trace route question - Loyer, Jeff
[SI-LIST] Re: AC Coupling and Differential Pair's Termination - Paul Levin
[SI-LIST] Re: AC Coupling and Differential Pair's Termination - Loyer, Jeff
[SI-LIST] Help:Who has these models? - Zhangmin Zhong
[SI-LIST] Re: Help:Who has these models? - eric . rushbrook
[SI-LIST] [SI-LIST]Same Pin Number connected to more than one net. - Alicia Corrales Chanca
[SI-LIST] Occurrence-specific properties on SCHEMATIC1/V1, ignoring - Alicia Corrales Chanca
[SI-LIST] Re: Interfacing Single ended PECL signal to differential PECL pair - Ingraham, Andrew
[SI-LIST] Re: AC Coupling and Differential Pair's Termination - Ingraham, Andrew
[SI-LIST] Re: Occurrence-specific properties on SCHEMATIC1/V1, ignoring - Bill Dempsey
[SI-LIST] Re: Pick & Place Machines operation - Erhan Kaya
[SI-LIST] Help on Mentor Graphic's ICX Tool - Shiraz Bashir
[SI-LIST] Re: Need a tool to calculate trace inductance. - ttsp
[SI-LIST] Re: Need a tool to calculate trace inductance. - Ray Anderson
[SI-LIST] Re: Need a tool to calculate trace inductance. - cadpro2k
[SI-LIST] Re: Need a tool to calculate trace inductance. - Chris Cheng
[SI-LIST] Re: SMA replacement - Kikito Vertiginopulos
[SI-LIST] Re: W-element - Dmitri Kuznetsov
[SI-LIST] MODEL SELECT -- In IBIS and XTK - Siva kumar
[SI-LIST] Re: input capacitance representation in IBIS - PRIEUR, Olivier
[SI-LIST] EM simulator software? - Rafael Martinez
[SI-LIST] Re: EM simulator software? - D G
[SI-LIST] Re: EM simulator software? - Jason Roth
[SI-LIST] pwr-gnd loop inductance measurment - Jean Audet
[SI-LIST] Re: EM simulator software? - ttsp
[SI-LIST] Re: EM simulator software? - Vadim Heyfitch
[SI-LIST] Re: pwr-gnd loop inductance measurment - Clewell, Craig
[SI-LIST] Re: input capacitance representation in IBIS - Tom Dagostino
[SI-LIST] Pads layout to HSPICE postroute - Siva kumar
[SI-LIST] Re: Interfacing Single ended PECL signal to differenti - Steven Kan
[SI-LIST] Re: Why we need to use "Series resistor" at Transmitter ? - Paliakara, Vinod
[SI-LIST] Re: Why we need to use "Series resistor" at Transmitter ? - Michael Nudelman
[SI-LIST] Re: pwr-gnd loop inductance measurment - Ray Anderson
[SI-LIST] Re: Why we need to use "Series resistor"atTransmitter ? - Abhijit Mahajan
[SI-LIST] Re: EM simulator software? - Scott McMorrow
[SI-LIST] Re: pwr-gnd loop inductance measurment - Clewell, Craig
[SI-LIST] Re: Why we need to use "Series resistor" at Transmitter ? - Ingraham, Andrew
[SI-LIST] Re: pwr-gnd loop inductance measurment - Chris Cheng
[SI-LIST] Multi-Plane Equivalent Capacitance in BGA Package - porshs
[SI-LIST] Re: pwr-gnd loop inductance measurment - Krina Kothari
[SI-LIST] Re: EM simulator software? - Perry Qu
[SI-LIST] Re: pwr-gnd loop inductance measurment - Ray Anderson
[SI-LIST] Reaching 2 Gbps out of a single-ended interface - Stephane Tremblay
[SI-LIST] Re: Why we need to use "Series resistor" at Transmitter ? - Ray Anderson
[SI-LIST] Re: Reaching 2 Gbps out of a single-ended interface - Scott McMorrow
[SI-LIST] Actual experience with LVDS to optical serializers with LVPECL inputs - Aguiņaga
[SI-LIST] IBIS Seminar - Lynne Green
[SI-LIST] Re: Why we need to use "Series resistor" at Transmitter? - Scott McMorrow
[SI-LIST] Re: EM simulator software? - Swanson, Dan
[SI-LIST] Re: Reaching 2 Gbps out of a single-ended interface - Jean Audet
[SI-LIST] pwr-gnd loop inductance measurement - Eric Bogatin
[SI-LIST] Re: pwr-gnd loop inductance measurment - Jean Audet
[SI-LIST] Re: Reaching 2 Gbps out of a single-ended interface - Michael J. Degerstrom
[SI-LIST] Re: Reaching 2 Gbps out of a single-ended interface - Jean Audet
[SI-LIST] Re: Reaching 2 Gbps out of a single-ended interface - Stephane Tremblay
[SI-LIST] Re: Reaching 2 Gbps out of a single-ended interface - Jean Audet
[SI-LIST] Re: [IBIS] IBIS Seminar - Lynne Green
[SI-LIST] Re: [IBIS] IBIS Seminar - Tom Dagostino
[SI-LIST] Re: input capacitance representation in IBIS - Ravinder Ajmani
[SI-LIST] Re: input capacitance representation in IBIS - ruston, matt
[SI-LIST] Re: EM simulator software? - Pat Diao
[SI-LIST] Re: [IBIS] IBIS Seminar - Michael_Greim
[SI-LIST] Re: Reaching 2 Gbps out of a single-ended interface - Stephane Tremblay
[SI-LIST] Re: pwr-gnd loop inductance measurement - Chris Cheng
[SI-LIST] Re: Actual experience with LVDS to optical serializers with LVPECL inputs - Muhammad Sagarwala
[SI-LIST] Re: Reaching 2 Gbps out of a single-ended interface - Bill . Cohen
[SI-LIST] Re: [IBIS] IBIS Seminar - Raymond . Leung
[SI-LIST] About via model! - Jack W.C. Lin
[SI-LIST] Re: Interfacing Single ended PECL signal to differenti - Prasanna Nambi
[SI-LIST] SPARTAN IIE Voltage regulator selection - Ismail B - CTD, Chennai.
[SI-LIST] Antw: SPARTAN IIE Voltage regulator selection - Robert Nowak
[SI-LIST] Re: input capacitance representation in IBIS - Robert Haller
[SI-LIST] Re: SPARTAN IIE Voltage regulator selection - Ed Miguel
[SI-LIST] how to derive eye diagram - Moby Abraham
[SI-LIST] Re: SPARTAN IIE Voltage regulator selection - Tegan Campbell
[SI-LIST] Determining load line for LVDS IBIS Device - Timothy Coyle
[SI-LIST] Re: SPARTAN IIE Voltage regulator selection - plawler
[SI-LIST] Re: Determining load line for LVDS IBIS Device - Beal, Weston
[SI-LIST] Re: Multi Board Simulation with DIMM Board from Micron Tech - tcrondeau
[SI-LIST] Re: SPARTAN IIE Voltage regulator selection - Prasanna Nambi
[SI-LIST] Re: High-Speed Communications Alliance - jeff_latourrette
[SI-LIST] ODD Power Splitter - Julio
[SI-LIST] Max curent allowed in solder ball - Moses Chan
[SI-LIST] Re: ODD Power Splitter - ray_waugh
[SI-LIST] Re: ODD Power Splitter - Ingraham, Andrew
[SI-LIST] Re: SPARTAN IIE Voltage regulator selection - Ruturaj Pathak
[SI-LIST] The maximum length of a bus? - C.Y. Cheng
[SI-LIST] spice model of tantalum capacitor - Zhangkun
[SI-LIST] Re: The maximum length of a bus? - Zhangkun
[SI-LIST] Re: spice model of tantalum capacitor - istvan novak
[SI-LIST] Re: The maximum length of a bus? - C.Y. Cheng
[SI-LIST] LVPECL to 1.8V HSTL Conversion - Jineshwari B - CTD, Chennai.
[SI-LIST] Recall: LVPECL to 1.8V HSTL Conversion - Jineshwari B - CTD, Chennai.
[SI-LIST] Re: spice model of tantalum capacitor - michael . g . mcdermott
[SI-LIST] Re: EM simulator software? - Zhou, Xingling (Mick)
[SI-LIST] LVPECL to 1.8V HSTL Conversion - Jineshwari B - CTD, Chennai.
[SI-LIST] Re: LVPECL to 1.8V HSTL Conversion - Ingraham, Andrew
[SI-LIST] Re: LVPECL to 1.8V HSTL Conversion - Ingraham, Andrew
[SI-LIST] Re: Why we need to use "Series resistor" at Transmitter? - Jim Roberts
[SI-LIST] Re: Why we need to use "Series resistor" at Transmitter? - Ray Anderson
[SI-LIST] Re: Why we need to use "Series resistor" at Transmitter? - pwelling
[SI-LIST] Re: Why we need to use "Series resistor" at Transmitter? - Charles Hill
[SI-LIST] New Buried Capacitance Material - Zenklusen, Fred
[SI-LIST] Re: Why we need to use "Series resistor" at Transmitter? - Sandor Daranyi
[SI-LIST] Re: New Buried Capacitance Material - Zenklusen, Fred
[SI-LIST] Re: About via model! - Dr. Howard Johnson
[SI-LIST] help! hold time calculation of source synchronous timing - =?big5?b?SG91S2V2aW4oq0ql/qaoKQ==?=
[SI-LIST] Re: help! hold time calculation of source synchronous timing - =?big5?b?SG91S2V2aW4oq0ql/qaoKQ==?=
[SI-LIST] Re: help! hold time calculation of source synchronous timing - =?big5?b?SG91S2V2aW4oq0ql/qaoKQ==?=
[SI-LIST] Re: About via model! - Michael Khusid
[SI-LIST] Re: New Buried Capacitance Material - Ritchey Lee
[SI-LIST] Re: Why we need to use "Series resistor" at Transmitter? - Ritchey Lee
[SI-LIST] Re: Why we need to use "Series resistor" at Transmitter? - Robert Kezer
[SI-LIST] Re: Why we need to use "Series resistor" at Transmi tter? - Gupta, Deepali
[SI-LIST] Re: Why we need to use "Series resistor" at Transmitter? - Scott McMorrow
[SI-LIST] Re: Why we need to use "Series resistor" atTransmitter? - Bill Reams
[SI-LIST] Re: How to connect to GND planes - Stephane Tremblay
[SI-LIST] Re: Why we need to use "Series resistor" at Transmitter? - Chris Cheng
[SI-LIST] Re: Why we need to use "Series resistor" at Transmitter? - Ingraham, Andrew
[SI-LIST] Re: How to connect to GND planes - James_R_Jones
[SI-LIST] Re: How to connect to GND planes - Peter Arnold
[SI-LIST] Re: Why we need to use "Series resistor" at Transmitter? - Chris Cheng
[SI-LIST] Re: New Buried Capacitance Material - Ritchey Lee
[SI-LIST] Agilent HPFC5200D or Tachyon XLII - Ritchey Lee
[SI-LIST] Re: SPARTAN IIE Voltage regulator selection - Adam Barnes
[SI-LIST] IBIS model generation from Datasheet? How? - Inmyung Song
[SI-LIST] Re: IBIS model generation from Datasheet? How? - Tom Dagostino
[SI-LIST] ESD shielding of the board - Roger_Wu
[SI-LIST] spatial resolution and effective rise time of VNA with TDR time-domainoption - Jan Vercammen
[SI-LIST] Re: spatial resolution and effective rise time of VNA with TDR time-domain option - istvan novak
[SI-LIST] spice math question - John Ellis
[SI-LIST] Re: Why we need to use "Series resistor" at Transmitter? - Lieby David
[SI-LIST] Re: spice math question - Ingraham, Andrew
[SI-LIST] Re: Why we need to use "Series resistor" at Transmitter? - Jim Roberts
[SI-LIST] Re: spice math question - John Ellis
[SI-LIST] Re: How to connect to GND planes - Jim Roberts
[SI-LIST] Re: spatial resolution and effective rise time of VNA with TDR time-domain option - Dima Smolyansky
[SI-LIST] Re: spatial resolution and effective rise time of VNA with TDR time-domain option - Jim Roberts
[SI-LIST] Re: spice math question - John Ellis
[SI-LIST] Re: spice math question - Loyer, Jeff
[SI-LIST] Re: spatial resolution and effective rise time of VNA with TDR time-domain option - Istvan Novak - Board Design Technology
[SI-LIST] Re: spice math question - Ingraham, Andrew
[SI-LIST] Re: Why we need to use "Series resistor" at Transmitter? - Chris Cheng
[SI-LIST] Re: Why we need to use "Series resistor" at Transmi tter? - pwelling
[SI-LIST] Re: spatial resolution and effective rise time of VNA with TDR time-domain option - Lewandowski, Bob
[SI-LIST] Re: Routing a 125MHz bus with 1 Bidir, 2 Rcvrs and an input vector - Douglas Burns
[SI-LIST] Re: spatial resolution and effective rise time of VNA with TDR time-domain option - Loyer, Jeff
[SI-LIST] Re: spatial resolution and effective rise time of VNA with TDR time-domain option - D G
[SI-LIST] Re: spatial resolution and effective rise time of VNA with TDR time-domain option - D G
[SI-LIST] FET Probe - James_R_Jones
[SI-LIST] Re: FET Probe - Doug Smith
[SI-LIST] Xilinx Virtex2 driver spice models - Fasig, Jonathan L.
[SI-LIST] Re: FET Probe - Ingraham, Andrew
[SI-LIST] Re: spatial resolution and effective rise time of VNA with TDR time-domain option - Lewandowski, Bob
[SI-LIST] Re: spatial resolution and effective rise time of VNA with TDR time-domain option - Ely, Richard
[SI-LIST] Re: FET Probe - Ravinder Ajmani