FreeLists / si-list / [SI-LIST] Re: IBIS Model for Freescale MC68302

["Doug Burns" <dburns@xxxxxxxxxx>]

Mohit,

The first thing to do is a paper timing analysis to determine your basic 
setup/hold margins. This analysis will give you
an idea of how critical an accurate analysis is. If you have lots of margin, 
then using good "rules of thumb" for your
design should be fine. In this scenario, you could even use idealize driver 
models of the proper impedance and slew-rate
to show you what the signal quality may look like.

If however, the margins look tight (due to large Tco and setup/hold windows or 
that you know your bus has multiple loads
and is long), then simulation is a good idea. If you have spice models, SiSoft 
provides a Spice-to IBIS conversion
service at very reasonable rates. If you can not get the spice models, Then 
Teraspeed consulting group has the
capabilities to develop a good IBIS model from actual components.

Best regards,

Doug


Douglas J. Burns
Vice President, Consulting Services
Signal Integrity Software, Inc.
6 Clock Tower Place
Maynard, MA  01754
978-461-0449 x14
dburns@xxxxxxxxxx
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On 
Behalf Of mohit jain
Sent: Sunday, September 09, 2007 3:12 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] IBIS Model for Freescale MC68302

Hi All,
I am doing the SI analysis of the design which has MC68302 processor TQFP144
Package running at 12MHz.
IBIS model of this processor is not available on the website, nor I could
find all the parameters that are requied for the IBIS model in the datasheet.


With other equivalent models I am not able to simulate properly, please
suggest some equivalent IBIS modeI for the same.

Thanks in advance.

Mohit Jain
Design Engineer
R&D Services
MindTree Consulting Pvt. Ltd.


      
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