FreeLists / si-list / [SI-LIST] Re: Testing chips with system level specs

[Doug Smith <doug@xxxxxxxxxx>]

Hi David,

I use the Fischer F-65 for convenience. It has about a 1 MHz to 1 GHz 
flat bandwidth and a one Ohm transfer impedance (1 V/A). With it I can 
measure current into real circuits/devices as well as ground planes.

Many current probes have too much E-field sensitivity for use around 
ESD. Back at Bell Labs, I noticed a CT-1 had a significant E-field 
response (resulting in a 25% error in the displayed waveform). The 
problem is current probes are sometimes designed for a relatively low 
impedance environment like 50 Ohms. ESD often has a much higher 
E-field to H-field ratio and the shielding of the probe becomes very 
important.

One "null experiment" is to solder a perpendicular stub on the current 
carrying wire and put the current probe around it. Then clip the stub 
off so it does not extend pass the current probe. If you read a lot of 
current, the shielding in the probe is suspect. You can also fold the 
current carrying wire and insert into the probe, although for fast 
waveforms like ESD this may affect the current more.

Another "null experiment" is to flip the current probe on the wire. 
The waveform should just flip as well. If it looks different other 
than inverted phase, the difference is the E-field coupling.

Doug

David Cuthbert wrote:

> Hi Doug,
> 
> The faster risetimes were obtained while holding a tool in my hand. I used
> myself for these discharges up to 8 kV - a rather unpleasant ESD voltage. I
> was standing on a metal mat, if I remember correctly. 
> 
> As all of this was done at another employer, and as I do not take notes with
> me, it all must be recreated. My aim here is to help make sure that the test
> standards reflect reality. It wouldn't do for devices to be designed to
> incorrect specfications that ultimately yielded problems in the field or
> expensive over-engineering. Either case is an extra cost to society that can
> be avoided. 
> 
> A case in point is the ESD protection structure that is dv/dt triggered.
> Design this to require too high of a dv/dt and it might be ineffective in
> the field. It would also be nice to histogram actual ESD events to that
> engineers can design in ESD protection to 3 standard deviations, for
> example.
> 
> I notice that in your test fixture you use what appears to be a Pearson
> current viewing transformer. Others use the Tektronix CT-6 or CT-3(?)
> current viewing transformer. I used a 'Pelligrini' target (invented by a
> member of this reflector who happens to not have the name Pelligrini). The
> target I used is detailed in Conformity magazine at this link:
> 
> http://www.conformity.com/0504/0504simple.html
> 
> I'm interested in continuing these studies of ESD and would be glad to
> collaborate with others. 
> 
> I am interested in moving TLP testing to the device level. I believe that
> this would yield better testing. Once the 1500 ohm ESD gun is applied to a
> PCB and the signal traverses several inches of transmission line, it is a
> different animal. 
> 
>     Dave Cuthbert
> 
> 
> 
> -----Original Message-----
> From: Doug Smith [mailto:doug@xxxxxxxxxx] 
> Sent: Tuesday, September 05, 2006 7:17 PM
> To: dcuthbert@xxxxxxxxxx
> Cc: doug@xxxxxxxxxx; davidjp@xxxxxxx; 'SI-List'; 'emc-pstc'
> Subject: Re: [SI-LIST] Re: Testing chips with system level specs
> 
> Hi David,
> 
> It is good to have lots of discussion on this. ESD is often only 
> considered when a gross problem surfaces. This discussion will help 
> bring the issue to the front.
> 
> What voltages were you using? Such fast events are common at low 
> voltages and rare at high voltages. I have personally measured edges 
> of <80 picoseconds at low voltages. For my chip example where slow 
> approach (say plugging in a memory card into a reader) is the norm, a 
> fast edge is probably not possible although I do not have 
> comprehensive data on this.
> 
> It seems one has to work at it to get a fast discharge at high 
> voltages, at least that is what I read through the lines. Hish et.al. 
> in a 1991 paper show three waveforms at about 10 kV, two slow and one 
> fast, but again they used a specific conical shaped tip with symmetry 
> that was required (that part was not spelled out clearly in the paper 
> but I was talking with a friend of Andy's). They said the likelihood 
> of the fast event was much smaller for a rounded tip.
> 
> Doug
> 
> David Cuthbert wrote:
> 
>>Doug,
>>
>>I've done some measurements of actual human body discharges into a 2 ohm
>>current target. The rise time was less than 500 ps. I plan to continue
> 
> this
> 
>>work soon using a 2.5 GHz oscilloscope and a TDR. The human SPICE model I
>>developed is quite interesting and I'll be refining it. 
>>
>>I then built a circuit that quite accurately mimics the actual human body
>>discharge. It is much more complex than the usual ESD gun network. 
>>
>>    Dave Cuthbert  
>>
>>
>>LINEAR TECHNOLOGY CORPORATION
>> 
>>
>>Internet Email Confidentiality Footer 
>>
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> 
> legally
> 
>>privileged. IF you are not the intended recipient, or a person responsible
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>>Thank You
>>
>>
>>
>>-----Original Message-----
>>From: emc-pstc@xxxxxxxx [mailto:emc-pstc@xxxxxxxx] On Behalf Of Doug Smith
>>Sent: Monday, September 04, 2006 11:15 AM
>>To: davidjp@xxxxxxx
>>Cc: SI-List; emc-pstc
>>Subject: Re: [SI-LIST] Re: Testing chips with system level specs
>>
>>Hi David and the group,
>>
>>You have presented good data which you and others have presented in 
>>the various standards bodies we have attended together. However, have 
>>you ever seen an air discharge with a 700 ps rise time at 8 kV? If so, 
>>what is the probability in the distribution of 8kV discharges? I 
>>measured a lot of discharges and none came close to that. Some had a 
>>vestige of the initial spike, but it was not much larger that the body 
>>discharge after and its risetime was always much slower.
>>
>>If this concept was to be included in a standard, a lot of work would 
>>be needed to determine the right amount of filtering.
>>
>>But, to apply this waveform (8 kV contact discharge) to a solid state 
>>device like a flash memory card is not justified and will needlessly 
>>increase device cost. I do agree that an 8kV contact discharge has 
>>uses in system level testing which what the 61000-4-2 standard was 
>>intended for.
>>
>>There is a LOT of work to apply that standard to devices, much more 
>>than the filtering I wrote about. There is no guidance in the standard 
>>as to how to apply the discharge and how it is applied will almost 
>>completely determine the results (other pins grounded or ungrounded, 
>>if grounded how, and much more).  If someone says their device passes 
>>this test, the statement is meaningless at this point unless the test 
>>method is documented.
>>
>>Doug
>>
>>Pommerenke, David wrote:
>>
>>
>>>Group,
>>>I like the idea from Doug to use a ferrite for reducing the risetime of a
>>
>>contact mode ESD generator. However, I do not agree to the statement that
>>air discharge ESD will not show fast risetimes and high peak values at
>>voltages above 4kV. The reference event for the ESD standard IEC 61000-4-2
>>is the discharge between a hand-held metal part and a large metallic
> 
> surface
> 
>>(called "hand-metal ESD") in contrast to the IC-HBM standard that is based
>>on a discharge from the skin.
>>
>>
>>>The current has two maxima, an initial peak caused by the charges on teh
>>
>>hand and on the metal part and the later body waveform. If the initial
> 
> peak
> 
>>will show up depends on the resistance of the arc as a function of time.
> 
> If
> 
>>the arc resistance drops quickly (let us say in less than 1ns) below the
>>source impedance of the discharging person (without going into details,
>>assume 100-300 Ohm http://web.umr.edu/~davidjp/paper/00478274.pdf ), then
>>the inital peak will show up. If the arc resistance drops slowly, let us
> 
> say
> 
>>it reaches 300 Ohm in 5 ns, then the initial peak will not show up, as the
>>arc resistance is too high during this phase of the discharge.
>>
>>
>>>So the quesion is: How fast does the arc resistance drop?
>>>
>>>This depends mainly on:
>>>
>>> - Voltage at the moment the discharge starts
>>> - Gap distance at the moment the discharge starts
>>>
>>>The smaller the gap, the faster the arc resistance will drop. The gaps
>>
>>will in most cases not discharge over distances given by the Paschen-law,
>>but at smaller distance. This is a result of the speed of appraoch and the
>>statistical time lag ().
>>
>>
>>>In general the behavior is as follows:
>>>
>>>  Fast rise times             ---      Slow rise times
>>>  
>>>   Fast approach                          slow approach
>>>   Dry air                                  Moist iar
>>>   Clean surfaces                           Dirty surfaces
>>>   Oxid layer, or paint  
>>>
>>>The effect of environmental conidtions on the discharge are very strong.
>>
>>Humidity dominates over all other influencing factors (I can email papers
> 
> on
> 
>>this topic on request). It is not possible to state: Above XYZ kV
> 
> discharges
> 
>>will not have an initial peak.
>>
>>
>>>To provide further evidence I attached a set of measurements that show the
>>
>>peak current as a function of voltage having the arc length as parameter.
>>The data is from D.Pommerenke, ESD: Transient fields, arc simulation and
>>rise time limits, Journal of Electrostatics, 36, 1995, 31-54.
>>
>>
>>>However, the likelyhood of having fast risetimes (e..g, less than 200ps)
>>
>>decreases above about 6-10 kV. Nobody knows the distribution of ESD
>>intensity in reality very well. There are a few studies, but they only
> 
> help
> 
>>to answer the question of voltage distribution, not of rise time
>>distribution or field strengths distribution.
>>
>>
>>>Overall, I warn against changing the pulse parameters above some voltage
>>
>>without having strong evidence that the reduction in protection level is
>>acceptable, the 0.7ns-1ns risetime is already providing only partial
>>coverage. 
>>
>>
>>>Products that may see many ESDs or support critical functions should
>>
>>certainly not be tested at a different waveform. The 0.7ns - 1ns rise time
>>standardized contact mode waveform certainly does not cover the faster ESD
>>events.
>>
>>
>>>Regards,
>>>
>>> David Pommerenke
>>>
>>>
>>>
>>>-----Original Message-----
>>>From: si-list-bounce@xxxxxxxxxxxxx on behalf of Doug Smith
>>>Sent: Sun 9/3/2006 11:03 PM
>>>To: SI-List; emc-pstc
>>>Subject: [SI-LIST] Testing chips with system level specs
>>>
>>>Hi All,
>>>
>>>I have been writing and recording again, this time on applying system 
>>>level ESD tests to devices. If you are involved with either devices 
>>>that can be handled by people (for instance a USB thumb drive for 
>>>flash memory card) or the equipment they plug into you will find my 
>>>latest article and podcast of interest. Any standards people out there?
>>>
>>>This month's Technical Tidbit describes a method to simulate air 
>>>discharges at voltages above 4 kV in a repeatable way using a modified 
>>>contact discharge. This method is especially useful in ESD testing of 
>>>solid state circuits using IEC 61000-4-2.
>>>
>>>Abstract: Contact discharge is used in ESD testing to improve test 
>>>repeatability, yet air discharge has significantly different 
>>>characteristics at higher voltages. A test method is described that 
>>>uses a modified contact discharge to simulate the characteristics of 
>>>an air discharge but with improved repeatability.
>>>
>>>The link to the article is the picture of the experimental test setup 
>>>at the bottom of the home page at http://emcesd.com . Or just click on 
>>>this link:
>>>
>>>http://emcesd.com/tt2006/tt090106.htm
>>>
>>>There is also an audio discussion of this article on my podcast site: 
>>>http://emcesd-podcast.com where the direct link to the audio file is:
>>>
>>>http://emcesd-podcast.com/2006/september/2006-0904.mp3
>>>
>>>Can't download mp3 files? Download the following instead:
>>>
>>>http://emcesd-podcast.com/2006/september/2006-0904.dcs
>>>
>>>After download, change the extension from .dcs to .mp3 and the file 
>>>will then be able to play on most computers.
>>>
>>>Doug
>>>
>>
>>
> 

-- 
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     ___          _       Doug Smith
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