
|
[si-list]
||
[Date Prev]
[09-2006 Date Index]
[Date Next]
||
[Thread Prev]
[09-2006 Thread Index]
[Thread Next]
[SI-LIST] Re: Testing chips with system level specs
- From: "David Cuthbert" <dcuthbert@xxxxxxxxxx>
- To: "'Grasso, Charles'" <Charles.Grasso@xxxxxxxxxxxx>, <doug@xxxxxxxxxx>
- Date: Wed, 6 Sep 2006 10:09:07 -0600
Charles,
I have not done any correlation between a 'real' pulse and the ESD gun. We
could assume that 'real' is sure to be better in all cases. Or, we can
correlate to a particular device and know is 'real' is better for that
device only.
I do not have a copy of the schematic of the more complex model. This I can
recreate quickly as soon as I get another ESD current target. I'll get on on
the way. The schematic will then find its way out of the messy filing
cabinet I call my mind.
Dave Cuthbert
-----Original Message-----
From: emc-pstc@xxxxxxxx [mailto:emc-pstc@xxxxxxxx] On Behalf Of Grasso,
Charles
Sent: Wednesday, September 06, 2006 9:07 AM
To: doug@xxxxxxxxxx; dcuthbert@xxxxxxxxxx
Cc: davidjp@xxxxxxx; SI-List; emc-pstc
Subject: RE: [SI-LIST] Re: Testing chips with system level specs
Hi David,
I am intrigued by the "more complex" model you built for
the ESD gun.
Question: Have you seen product that passes the EN61000-3-2
yet fails using your gun?
Best Regards
Charles Grasso
Compliance Engineer
Echostar Communications Corp.
Tel: 303-706-5467
Fax: 303-799-6222
Cell: 303-204-2974
Pager/Short Message: 3032042974@xxxxxxxxx
Email: charles.grasso@xxxxxxxxxxxx;
Email Alternate: chasgrasso@xxxxxxxx
-----Original Message-----
From: emc-pstc@xxxxxxxx [mailto:emc-pstc@xxxxxxxx] On Behalf Of Doug
Smith
Sent: Tuesday, September 05, 2006 7:17 PM
To: dcuthbert@xxxxxxxxxx
Cc: doug@xxxxxxxxxx; davidjp@xxxxxxx; 'SI-List'; 'emc-pstc'
Subject: Re: [SI-LIST] Re: Testing chips with system level specs
Hi David,
It is good to have lots of discussion on this. ESD is often only
considered when a gross problem surfaces. This discussion will help
bring the issue to the front.
What voltages were you using? Such fast events are common at low
voltages and rare at high voltages. I have personally measured edges
of <80 picoseconds at low voltages. For my chip example where slow
approach (say plugging in a memory card into a reader) is the norm, a
fast edge is probably not possible although I do not have
comprehensive data on this.
It seems one has to work at it to get a fast discharge at high
voltages, at least that is what I read through the lines. Hish et.al.
in a 1991 paper show three waveforms at about 10 kV, two slow and one
fast, but again they used a specific conical shaped tip with symmetry
that was required (that part was not spelled out clearly in the paper
but I was talking with a friend of Andy's). They said the likelihood
of the fast event was much smaller for a rounded tip.
Doug
David Cuthbert wrote:
> Doug,
>
> I've done some measurements of actual human body discharges into a 2
ohm
> current target. The rise time was less than 500 ps. I plan to continue
this
> work soon using a 2.5 GHz oscilloscope and a TDR. The human SPICE
model I
> developed is quite interesting and I'll be refining it.
>
> I then built a circuit that quite accurately mimics the actual human
body
> discharge. It is much more complex than the usual ESD gun network.
>
> Dave Cuthbert
>
>
> LINEAR TECHNOLOGY CORPORATION
>
>
> Internet Email Confidentiality Footer
>
> This e-mail transmission, and any documents, files or previous e-mail
> messages attached to it may contain confidential information that is
legally
> privileged. IF you are not the intended recipient, or a person
responsible
> for delivering it to the intended recipient, you are hereby notified
that
> any disclosure, copying, distribution or use of any of the information
> contain in or attached to this transmission is STRICTLY PROHIBITED. If
you
> have received this transmission in error, please immediately notify me
by
> reply e-mail, or by telephone at (719)593-1579,and destroy the
original
> transmission and its attachments without reading or saving in any
manner.
> Thank You
>
>
>
> -----Original Message-----
> From: emc-pstc@xxxxxxxx [mailto:emc-pstc@xxxxxxxx] On Behalf Of Doug
Smith
> Sent: Monday, September 04, 2006 11:15 AM
> To: davidjp@xxxxxxx
> Cc: SI-List; emc-pstc
> Subject: Re: [SI-LIST] Re: Testing chips with system level specs
>
> Hi David and the group,
>
> You have presented good data which you and others have presented in
> the various standards bodies we have attended together. However, have
> you ever seen an air discharge with a 700 ps rise time at 8 kV? If so,
> what is the probability in the distribution of 8kV discharges? I
> measured a lot of discharges and none came close to that. Some had a
> vestige of the initial spike, but it was not much larger that the body
> discharge after and its risetime was always much slower.
>
> If this concept was to be included in a standard, a lot of work would
> be needed to determine the right amount of filtering.
>
> But, to apply this waveform (8 kV contact discharge) to a solid state
> device like a flash memory card is not justified and will needlessly
> increase device cost. I do agree that an 8kV contact discharge has
> uses in system level testing which what the 61000-4-2 standard was
> intended for.
>
> There is a LOT of work to apply that standard to devices, much more
> than the filtering I wrote about. There is no guidance in the standard
> as to how to apply the discharge and how it is applied will almost
> completely determine the results (other pins grounded or ungrounded,
> if grounded how, and much more). If someone says their device passes
> this test, the statement is meaningless at this point unless the test
> method is documented.
>
> Doug
>
> Pommerenke, David wrote:
>
>>Group,
>>I like the idea from Doug to use a ferrite for reducing the risetime
of a
>
> contact mode ESD generator. However, I do not agree to the statement
that
> air discharge ESD will not show fast risetimes and high peak values at
> voltages above 4kV. The reference event for the ESD standard IEC
61000-4-2
> is the discharge between a hand-held metal part and a large metallic
surface
> (called "hand-metal ESD") in contrast to the IC-HBM standard that is
based
> on a discharge from the skin.
>
>>The current has two maxima, an initial peak caused by the charges on
teh
>
> hand and on the metal part and the later body waveform. If the initial
peak
> will show up depends on the resistance of the arc as a function of
time. If
> the arc resistance drops quickly (let us say in less than 1ns) below
the
> source impedance of the discharging person (without going into
details,
> assume 100-300 Ohm http://web.umr.edu/~davidjp/paper/00478274.pdf ),
then
> the inital peak will show up. If the arc resistance drops slowly, let
us say
> it reaches 300 Ohm in 5 ns, then the initial peak will not show up, as
the
> arc resistance is too high during this phase of the discharge.
>
>>So the quesion is: How fast does the arc resistance drop?
>>
>>This depends mainly on:
>>
>> - Voltage at the moment the discharge starts
>> - Gap distance at the moment the discharge starts
>>
>>The smaller the gap, the faster the arc resistance will drop. The gaps
>
> will in most cases not discharge over distances given by the
Paschen-law,
> but at smaller distance. This is a result of the speed of appraoch and
the
> statistical time lag ().
>
>>In general the behavior is as follows:
>>
>> Fast rise times --- Slow rise times
>>
>> Fast approach slow approach
>> Dry air Moist iar
>> Clean surfaces Dirty surfaces
>> Oxid layer, or paint
>>
>>The effect of environmental conidtions on the discharge are very
strong.
>
> Humidity dominates over all other influencing factors (I can email
papers on
> this topic on request). It is not possible to state: Above XYZ kV
discharges
> will not have an initial peak.
>
>>To provide further evidence I attached a set of measurements that show
the
>
> peak current as a function of voltage having the arc length as
parameter.
> The data is from D.Pommerenke, ESD: Transient fields, arc simulation
and
> rise time limits, Journal of Electrostatics, 36, 1995, 31-54.
>
>>However, the likelyhood of having fast risetimes (e..g, less than
200ps)
>
> decreases above about 6-10 kV. Nobody knows the distribution of ESD
> intensity in reality very well. There are a few studies, but they only
help
> to answer the question of voltage distribution, not of rise time
> distribution or field strengths distribution.
>
>>Overall, I warn against changing the pulse parameters above some
voltage
>
> without having strong evidence that the reduction in protection level
is
> acceptable, the 0.7ns-1ns risetime is already providing only partial
> coverage.
>
>>Products that may see many ESDs or support critical functions should
>
> certainly not be tested at a different waveform. The 0.7ns - 1ns rise
time
> standardized contact mode waveform certainly does not cover the faster
ESD
> events.
>
>>Regards,
>>
>> David Pommerenke
>>
>>
>>
>>-----Original Message-----
>>From: si-list-bounce@xxxxxxxxxxxxx on behalf of Doug Smith
>>Sent: Sun 9/3/2006 11:03 PM
>>To: SI-List; emc-pstc
>>Subject: [SI-LIST] Testing chips with system level specs
>>
>>Hi All,
>>
>>I have been writing and recording again, this time on applying system
>>level ESD tests to devices. If you are involved with either devices
>>that can be handled by people (for instance a USB thumb drive for
>>flash memory card) or the equipment they plug into you will find my
>>latest article and podcast of interest. Any standards people out
there?
>>
>>This month's Technical Tidbit describes a method to simulate air
>>discharges at voltages above 4 kV in a repeatable way using a modified
>>contact discharge. This method is especially useful in ESD testing of
>>solid state circuits using IEC 61000-4-2.
>>
>>Abstract: Contact discharge is used in ESD testing to improve test
>>repeatability, yet air discharge has significantly different
>>characteristics at higher voltages. A test method is described that
>>uses a modified contact discharge to simulate the characteristics of
>>an air discharge but with improved repeatability.
>>
>>The link to the article is the picture of the experimental test setup
>>at the bottom of the home page at http://emcesd.com . Or just click on
>>this link:
>>
>>http://emcesd.com/tt2006/tt090106.htm
>>
>>There is also an audio discussion of this article on my podcast site:
>>http://emcesd-podcast.com where the direct link to the audio file is:
>>
>>http://emcesd-podcast.com/2006/september/2006-0904.mp3
>>
>>Can't download mp3 files? Download the following instead:
>>
>>http://emcesd-podcast.com/2006/september/2006-0904.dcs
>>
>>After download, change the extension from .dcs to .mp3 and the file
>>will then be able to play on most computers.
>>
>>Doug
>>
>
>
--
------------------------------------------------------------
___ _ Doug Smith
\ / ) P.O. Box 1457
========= Los Gatos, CA 95031-1457
_ / \ / \ _ TEL/FAX: 408-356-4186/358-3799
/ /\ \ ] / /\ \ Mobile: 408-858-4528
| q-----( ) | o | Email: doug@xxxxxxxxxx
\ _ / ] \ _ / Web: http://www.dsmith.org
------------------------------------------------------------
-
----------------------------------------------------------------
This message is from the IEEE Product Safety Engineering Society
emc-pstc discussion list. Website: http://www.ieee-pses.org/
To post a message to the list, send your e-mail to emc-pstc@xxxxxxxx
Instructions: http://listserv.ieee.org/request/user-guide.html
List rules: http://www.ieee-pses.org/listrules.html
For help, send mail to the list administrators:
Scott Douglas emcpstc@xxxxxxxxx
Mike Cantwell mcantwell@xxxxxxxx
For policy questions, send mail to:
Jim Bacher: j.bacher@xxxxxxxx
David Heald: emc-pstc@xxxxxxxxxxxxx
All emc-pstc postings are archived and searchable on the web at:
http://www.ieeecommunities.org/emc-pstc
-
----------------------------------------------------------------
This message is from the IEEE Product Safety Engineering Society
emc-pstc discussion list. Website: http://www.ieee-pses.org/
To post a message to the list, send your e-mail to emc-pstc@xxxxxxxx
Instructions: http://listserv.ieee.org/request/user-guide.html
List rules: http://www.ieee-pses.org/listrules.html
For help, send mail to the list administrators:
Scott Douglas emcpstc@xxxxxxxxx
Mike Cantwell mcantwell@xxxxxxxx
For policy questions, send mail to:
Jim Bacher: j.bacher@xxxxxxxx
David Heald: emc-pstc@xxxxxxxxxxxxx
All emc-pstc postings are archived and searchable on the web at:
http://www.ieeecommunities.org/emc-pstc
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List FAQ wiki page is located at:
http://si-list.org/wiki/wiki.pl?Si-List_FAQ
List technical documents are available at:
http://www.si-list.org
List archives are viewable at:
http://www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
|

|