Date Index for si-list, 09-2006

[si-list] || [09-2006 Date Index] [09-2006 Thread Index]

[SI-LIST] Re: What do you do? - Lynne D. Green
[SI-LIST] Re: May I know how can I check the ibis model from vendor - Lynne D. Green
[SI-LIST] Asian IBIS Summit (Japan) Announcement - Mirmak, Michael
[SI-LIST] About Generator short circuit current for EIA/TIA-644(LVDS) specification - wbchen . karen
[SI-LIST] About Generator short circuit current for EIA/TIA-644(LVDS) specification - wbchen . karen
[SI-LIST] stocksubj2 - Peggy Thurman
[SI-LIST] Current Bias Chip - Srivats Partha
[SI-LIST] Re: Timing equations - help - hreidmarkailen
[SI-LIST] Impedance without a reference plane - Bharathkumar Raju
[SI-LIST] Re: Impedance without a reference plane - Istvan Novak
[SI-LIST] Re: Current Bias Chip - Andrew Ingraham
[SI-LIST] Re: Timing equations - help - Andrew Ingraham
[SI-LIST] Testing chips with system level specs - Doug Smith
[SI-LIST] Re: Testing chips with system level specs - Pommerenke, David
[SI-LIST] Re: Impedance without a reference plane - nagaraj
[SI-LIST] Re: Testing chips with system level specs - Xilei Liu
[SI-LIST] Re: Testing chips with system level specs - Doug Smith
[SI-LIST] Re: What is the acceptable minimum pre-preg thickness for volume manufacturing? - Lee Ritchey
[SI-LIST] AW: Re: Testing chips with system level specs - Pommerenke, David
[SI-LIST] Re: What is the acceptable minimum pre-preg thickness for volume manufacturing? - Kenneth W. Egan
[SI-LIST] Re: Impedance without a reference plane - Ihsan Erdin
[SI-LIST] Re: Impedance without a reference plane - chand basha
[SI-LIST] Re: What is the acceptable minimum pre-preg thickness for volume manufacturing? - steve weir
[SI-LIST] Re: What is the acceptable minimum pre-pregthickness for volume manufacturing? - Lee Ritchey
[SI-LIST] Re: Testing chips with system level specs - David Cuthbert
[SI-LIST] Re: What is the acceptable minimum pre-pregthickness for volume manufacturing? - Salkow, Steven
[SI-LIST] Re: What is the acceptable minimum pre-pregthickness for volume manufacturing? - Aubrey_Sparkman
[SI-LIST] Re: What is the acceptable minimum pre-pregthickness for volume manufacturing? - B Simonovich
[SI-LIST] EU RoHS' (lead free initiative) effect on SI - Bashir, Shiraz \(GE Healthcare\)
[SI-LIST] We need help - Hill, John
[SI-LIST] Re: We need help - steve weir
[SI-LIST] Re: EU RoHS' (lead free initiative) effect on SI - Matthias Mansfeld
[SI-LIST] Re: ddr2 timing simulation - Kai Keskinen
[SI-LIST] Re: Testing chips with system level specs - Doug Smith
[SI-LIST] SI related jobs at Mobilygen; - Mark Apton
[SI-LIST] minimum and maximum tracelength - Vignesh Upadhyay
[SI-LIST] Out of office - Svein Medhus
[SI-LIST] Out of office - Svein Medhus
[SI-LIST] Re: minimum and maximum tracelength - Scott McMorrow
[SI-LIST] Re: minimum and maximum tracelength - chand basha
[SI-LIST] Re: minimum and maximum tracelength - Hiten Bhagat
[SI-LIST] Re: minimum and maximum tracelength - steve weir
[SI-LIST] which type of power(core logic power or I/O power) has a high priority - z46147
[SI-LIST] Re: minimum and maximum tracelength - kranthi
[SI-LIST] Re: which type of power(core logic power or I/O power) has a high priority - chand basha
[SI-LIST] Re: Testing chips with system level specs - Pommerenke, David
[SI-LIST] for you to have it GCM E - canadian
[SI-LIST] Re: Testing chips with system level specs - Grasso, Charles
[SI-LIST] Re: Testing chips with system level specs - Grasso, Charles
[SI-LIST] Re: Testing chips with system level specs - Pommerenke, David
[SI-LIST] Re: Testing chips with system level specs - Pommerenke, David
[SI-LIST] Out of office - Svein Medhus
[SI-LIST] Re: EU RoHS' (lead free initiative) effect on SI - B Simonovich
[SI-LIST] Re: Testing chips with system level specs - David Cuthbert
[SI-LIST] Re: Testing chips with system level specs - Sterner, David [S&FS]
[SI-LIST] Re: Testing chips with system level specs - Conway, Patrick R (Houston)
[SI-LIST] Out of office - Svein Medhus
[SI-LIST] Re: Testing chips with system level specs - David Cuthbert
[SI-LIST] some help needed: Re: Testing chips with system level specs - Pommerenke, David
[SI-LIST] Re: some help needed: Re: Testing chips with system level specs - Grasso, Charles
[SI-LIST] Re: We need help - Salkow, Steven
[SI-LIST] Out of office - Svein Medhus
[SI-LIST] Re: We need help - steve weir
[SI-LIST] Re: What is the acceptable minimum pre-pregthickness for volume manufacturing? - George Dudnikov
[SI-LIST] Re: What is the acceptable minimum pre-pregthickness for volume manufacturing? - steve weir
[SI-LIST] How to get RLC equivalent model from S parameter of the passive component - fei xue
[SI-LIST] Re: How to get RLC equivalent model from S parameter of the passive component - steve weir
[SI-LIST] fwd: Watch PPTL on Thursday September 7, 2006 - Truman Cooke
[SI-LIST] Out of office - Svein Medhus
[SI-LIST] Out of office - Svein Medhus
[SI-LIST] Fw: OT: SPAM! - Andrew W. Riley III
[SI-LIST] Watch PPTL on Thursday Sep 7 - Donovan Dill
[SI-LIST] EBD Files - nrpatel
[SI-LIST] Re: Testing chips with system level specs - Doug Smith
[SI-LIST] Re: Testing chips with system level specs - Doug Smith
[SI-LIST] Re: Decoupling capacitors for BGA - Scott McMorrow
[SI-LIST] AMD Signal Integrity Job Opportunity - jworth
[SI-LIST] Re: What is the acceptable minimum pre-pregthickness for volume manufacturing? - Chris Cheng
[SI-LIST] Re: What is the acceptable minimum pre-pregthickness for volume manufacturing? - jworth
[SI-LIST] Re: Testing chips with system level specs - Doug Smith
[SI-LIST] Re: Decoupling capacitors for BGA - Mark Alexander
[SI-LIST] Re: What is the acceptable minimum pre-pregthickness for volume manufacturing? - Chris Cheng
[SI-LIST] Out of office - Svein Medhus
[SI-LIST] Re: Decoupling capacitors for BGA - Scott McMorrow
[SI-LIST] Re: Testing chips with system level specs - Grasso, Charles
[SI-LIST] Re: Decoupling capacitors for BGA - Mark Alexander
[SI-LIST] Re: What is the acceptable minimum pre-pregthickness for volume manufacturing? - George Dudnikov
[SI-LIST] PCIe load board - Chia, Ben
[SI-LIST] Voltage & Prepeg thickness - Sreekanth N nampoothiri
[SI-LIST] Out of office - Svein Medhus
[SI-LIST] Out of office - Svein Medhus
[SI-LIST] Antw: Voltage & Prepeg thickness - Robert Nowak
[SI-LIST] high voltage - RameshK Cozerv IN HO
[SI-LIST] HighVoltage - RameshK Cozerv IN HO
[SI-LIST] Re: Voltage & Prepeg thickness - Powell, Doug
[SI-LIST] ICEM model - Saoer Sinaga
[SI-LIST] Re: Voltage & Prepeg thickness - Curt McNamara
[SI-LIST] Re: HighVoltage - Muranyi, Arpad
[SI-LIST] Re: ICEM model - Syed Huq \(shuq\)
[SI-LIST] Re: Voltage & Prepeg thickness - Powell, Doug
[SI-LIST] Re: Voltage & Prepeg thickness - Curt McNamara
[SI-LIST] Do you use board-level signal integrity simulation? - rbmerrit
[SI-LIST] Re: What is the acceptable minimum pre-pregthickness for volume manufacturing? - George Dudnikov
[SI-LIST] Out of office - Svein Medhus
[SI-LIST] Out of office - Svein Medhus
[SI-LIST] Re: Setup-Hold Equations for Source Synchronous Design - hreidmarkailen
[SI-LIST] Re: Setup-Hold Equations for Source Synchronous Design - hreidmarkailen
[SI-LIST] Out of office - Svein Medhus
[SI-LIST] Out of office - Svein Medhus
[SI-LIST] Re: What is the acceptable minimum pre-pregthickness for volume manufacturing? - steve weir
[SI-LIST] PCB High Voltage - RameshK Cozerv IN HO
[SI-LIST] FW: PCB High Voltage - RameshK Cozerv IN HO
[SI-LIST] Pcb High Voltage - RameshK Cozerv IN HO
[SI-LIST] Pcb High Voltage - RameshK Cozerv IN HO
[SI-LIST] Re: FW: PCB High Voltage - RameshK Cozerv IN HO
[SI-LIST] Out of office - Svein Medhus
[SI-LIST] Out of office - Svein Medhus
[SI-LIST] Out of office - Svein Medhus
[SI-LIST] Emc_FTT - RameshK Cozerv IN HO
[SI-LIST] Emc-ftt - RameshK Cozerv IN HO
[SI-LIST] Measure flight time with TDR - Giuseppe DABUNDO
[SI-LIST] Re: What is the acceptable minimum pre-pregthickness for volume manufacturing? - Bill Wurst
[SI-LIST] Re: PCB High Voltage - Bill Wurst
[SI-LIST] Re: What is the acceptable minimum pre-pregthickness for volume manufacturing? - steve weir
[SI-LIST] Re: Measure flight time with TDR - Bill Wurst
[SI-LIST] Re: What is the acceptable minimum pre-pregthickness for volume manufacturing? - Bill Wurst
[SI-LIST] Re: Measure flight time with TDR - Tom Dagostino
[SI-LIST] List of PCB characterization/Modelling vendors in Bay Area - Jay Avula
[SI-LIST] Re: List of PCB characterization/Modelling vendors in Bay Area - Fabrizio . Zanella
[SI-LIST] Asian IBIS Summit (China) Fourth Announcement - Lance Wang
[SI-LIST] Emc_FTT - RameshK Cozerv IN HO
[SI-LIST] High voltage & via size - RameshK Cozerv IN HO
[SI-LIST] Consulting opportunity - Martin Euredjian
[SI-LIST] Emc_FTT - RameshK Cozerv IN HO
[SI-LIST] Emc_FTT - RameshK Cozerv IN HO
[SI-LIST] set SI-LIST vacation - Hirshtal Itzhak
[SI-LIST] Re: Voltage & Prepeg thickness - Hill, John
[SI-LIST] Re: What is the acceptable minimum pre-pregthickness for volume manufacturing? - George Dudnikov
[SI-LIST] Emc_FTT - RameshK Cozerv IN HO
[SI-LIST] Re: which type of power(core logic power or I/O power) has a high priority - Brad Crowell
[SI-LIST] Re: which type of power(core logic power or I/O power) has a high priority - steve weir
[SI-LIST] Re: Emc_FTT - Istvan Novak
[SI-LIST] Re: which type of power(core logic power or I/O power) has a high priority - Ken Cantrell
[SI-LIST] Re: which type of power(core logic power or I/O power) has a high priority - Brad Crowell
[SI-LIST] Re: which type of power(core logic power or I/O power) has a high priority - Ken Cantrell
[SI-LIST] Recommendation on a good HDI PCB proto house suitable for 0.5mm BGAs with SI - jeanpierrepoulin
[SI-LIST] Job Opening - Xilinx - Pat McGuire
[SI-LIST] Re: which type of power(core logic power or I/O power) has a high priority - Grasso, Charles
[SI-LIST] Re: Emc_FTT - Grasso, Charles
[SI-LIST] Re: Emc_FTT - Grasso, Charles
[SI-LIST] Asian IBIS Summit (Japan) Third Announcement - Mirmak, Michael
[SI-LIST] Emc_FTT - RameshK Cozerv IN HO
[SI-LIST] Re: Emc_FTT - steve weir
[SI-LIST] Re: which type of power(core logic power or I/O power) has a high priority - chand basha
[SI-LIST] Re: which type of power(core logic power or I/O power) has a high priority - steve weir
[SI-LIST] Routing Parallel vs. Paralell - Jack Olson
[SI-LIST] Re: Routing Parallel vs. Paralell - steve weir
[SI-LIST] Re: Routing Parallel vs. Paralell - Ken Cantrell
[SI-LIST] Re: Routing Parallel vs. Paralell - Xilei Liu
[SI-LIST] Re: Routing Parallel vs. Paralell - Beal, Weston
[SI-LIST] Re: Routing Parallel vs. Paralell - Jack Olson
[SI-LIST] Hspice: use S-Parameter model extracted from CST - Dorin Oprea
[SI-LIST] Re: Routing Parallel vs. Paralell - steve weir
[SI-LIST] Re: which type of power(core logic power or I/O power) has a high priority - chand basha
[SI-LIST] Re: Routing Parallel vs. Paralell - Xilei Liu
[SI-LIST] Post Layout Simulation - Coombs, William B. \(US SSA\)
[SI-LIST] Re: Routing Parallel vs. Paralell - Jack Olson
[SI-LIST] Re: Post Layout Simulation - Scott McMorrow
[SI-LIST] Spreading Inductance - Nash, Tim J \(EHCOE\)
[SI-LIST] Re: Routing Parallel vs. Paralell - Jack Olson
[SI-LIST] Re: Post Layout Simulation - Scott McMorrow
[SI-LIST] Signal Integrity Job Opportunities at Broadcom - Sam Karikalan
[SI-LIST] Re: Routing Parallel vs. Paralell - Jack Olson
[SI-LIST] Re: Routing Parallel vs. Paralell - Loyer, Jeff
[SI-LIST] Re: Post Layout Simulation - Kai Keskinen
[SI-LIST] Re: News for AMSN sun - Conrad Flores
[SI-LIST] Re: AMSN god - Lily Raines
[SI-LIST] Re: Spreading Inductance - Sirisha Godavarthy
[SI-LIST] Re: Hot monday dother - Shawn Bonds
[SI-LIST] Looking for Myun-Joo Park - Jason R. Miller
[SI-LIST] Re: Post Layout Simulation - Nitin Sood
[SI-LIST] OUTPUT IMPEDANCE CALCULATION [IBIS] - Carlos Toro
[SI-LIST] Re: OUTPUT IMPEDANCE CALCULATION [IBIS] - Scott McMorrow
[SI-LIST] Re: Spreading Inductance - steve weir
[SI-LIST] Re: Spreading Inductance - Sirisha Godavarthy
[SI-LIST] Target Impedance in PCB power plane... - Padmanaban Balamuraleedharan - TLS, Chennai
[SI-LIST] Re: Spreading Inductance - steve weir
[SI-LIST] Re: Target Impedance in PCB power plane... - steve weir
[SI-LIST] Re: Target Impedance in PCB power plane... - Padmanaban Balamuraleedharan - TLS, Chennai
[SI-LIST] Re: Target Impedance in PCB power plane... - steve weir
[SI-LIST] Re: OUTPUT IMPEDANCE CALCULATION [IBIS] - Peterson, James F \(EHCOE\)
[SI-LIST] Signal Integrity Engineering Manager - bruce harvie
[SI-LIST] hot-carrier effect on IC reliability - zhangkun 29902
[SI-LIST] Re: OUTPUT IMPEDANCE CALCULATION [IBIS] - Benny Yan
[SI-LIST] Rise time impact on input buffer - Padmanaban Balamuraleedharan - TLS, Chennai
[SI-LIST] Re: Rise time impact on input buffer - kranthi
[SI-LIST] Re: Rise time impact on input buffer - RameshK Cozerv IN HO
[SI-LIST] Re: Rise time impact on input buffer - Padmanaban Balamuraleedharan - TLS, Chennai
[SI-LIST] Re: OUTPUT IMPEDANCE CALCULATION [IBIS] - Peterson, James F \(EHCOE\)
[SI-LIST] DDR2 SO-DIMM Gerber files - Arai, Tadashi
[SI-LIST] Comments on PI analysis tools (Ansoft SI wave & Sigrity PI) - Yuming Tao
[SI-LIST] HSTL and SSTL - Arun Kumar
[SI-LIST] Re: DDR2 SO-DIMM Gerber files - Arai, Tadashi
[SI-LIST] Re: HSTL and SSTL - Bill . Cohen
[SI-LIST] Re: HSTL and SSTL - Abe (Abbas) Riazi
[SI-LIST] parallel plane strange results - Leonard Dieguez
[SI-LIST] Re: parallel plane strange results - Qazi Arif Iqbal
[SI-LIST] Re: parallel plane strange results - Leonard Dieguez
[SI-LIST] Memory Signal Integrity - Kenny Frohlich
[SI-LIST] Re: parallel plane strange results - Istvan Novak
[SI-LIST] Re: parallel plane strange results - steve weir
[SI-LIST] Re: Memory Signal Integrity - steve weir
[SI-LIST] Re: Memory Signal Integrity - Michael Rose
[SI-LIST] Digital Bench Characterization project in Sunnyvale - Kevin Pierpoint
[SI-LIST] Dual referenced stripline? - Christopher Rodenberg
[SI-LIST] Signal Integrity Wiki - Henry J. Campbell
[SI-LIST] Re: Signal Integrity Wiki - Ray Anderson
[SI-LIST] Re: parallel plane strange results - Guang Chen
[SI-LIST] Windows based IBIS Parser - Girish Chandra Mohanty
[SI-LIST] Re: Windows based IBIS Parser - Sreekanth N nampoothiri
[SI-LIST] di/dt transfer function measurement with Network Analyzer - jun feng
[SI-LIST] Re: di/dt transfer function measurement with Network Analyzer - steve weir
[SI-LIST] Intermittent issue with the board - Vignesh Upadhyay
[SI-LIST] Re: Intermittent issue with the board - steve weir
[SI-LIST] Re: Windows based IBIS Parser - Muranyi, Arpad
[SI-LIST] Re: Intermittent issue with the board - Hal Murray
[SI-LIST] Re: Intermittent issue with the board - hreidmarkailen
[SI-LIST] Rndom reset problem - Saril
[SI-LIST] Re: Spreading Inductance - Hill, John
[SI-LIST] Re: Spreading Inductance - steve weir
[SI-LIST] Re: Spreading Inductance - Hill, John
[SI-LIST] Re: Spreading Inductance - steve weir
[SI-LIST] Re: Dual referenced stripline? - ryansatrom
[SI-LIST] Re: Upcoming Class on SI and PCB Design at UC Berkeley - Lee Ritchey
[SI-LIST] Re: Spreading Inductance - Hill, John
[SI-LIST] Re: Spreading Inductance - steve weir
[SI-LIST] Re: Spreading Inductance - Hill, John
[SI-LIST] Re: Spreading Inductance - steve weir
[SI-LIST] Lossy Line Simulation DDR Signals and HSPICE netlist generation - Venkat
[SI-LIST] Re: Spreading Inductance - Peterson, James F \(EHCOE\)
[SI-LIST] DDR interface - Fraiman, Edi
[SI-LIST] Re: Spreading Inductance - Hill, John
[SI-LIST] Re: DDR interface - Fraiman, Edi
[SI-LIST] Re: Spreading Inductance - Scott McMorrow
[SI-LIST] Re: Spreading Inductance - steve weir
[SI-LIST] Asian IBIS Summit (China) - Fifth Announcement - Bob Ross
[SI-LIST] Question for CST Microwave Studio experts - Perry Qu
[SI-LIST] Re: Question for CST Microwave Studio experts - Scott McMorrow
[SI-LIST] Re: Question for CST Microwave Studio experts - Perry Qu
[SI-LIST] Q. on DDR rise time measurements - Grasso, Charles
[SI-LIST] Test - Grasso, Charles
[SI-LIST] Re: Question for CST Microwave Studio experts - Perry Qu
[SI-LIST] Re: DDR interface - Alex Li
[SI-LIST] Re: DDR interface - zheng qi
[SI-LIST] Re: DDR interface - sanjay kokitkar
[SI-LIST] Re: DDR interface - preetesh rathod
[SI-LIST] Re: DDR interface - preetesh rathod
[SI-LIST] Re: Rise time impact on input buffer - Andrew Ingraham
[SI-LIST] Re: DDR interface - Fraiman, Edi
[SI-LIST] An SI engineer you should know - rbmerrit
[SI-LIST] Re: An SI engineer you should know - Chris Cheng
[SI-LIST] Public Siemens IBIS website online - Lenski, Eckhard
[SI-LIST] FW: EPMC announcement - 2006 short course - Jin Zhao
[SI-LIST] Re: DDR interface - preetesh rathod
[SI-LIST] Public Siemens IBIS website online - Lenski, Eckhard
[SI-LIST] Aspect Ratio - RameshK Cozerv IN HO
[SI-LIST] Re: Aspect Ratio - ramakrishna raju
[SI-LIST] Re: Aspect Ratio - RameshK Cozerv IN HO
[SI-LIST] Aspect Ratio - RameshK Cozerv IN HO
[SI-LIST] Re: Aspect Ratio - Sreekanth N nampoothiri
[SI-LIST] Re: DDR interface - Peterson, James F \(EHCOE\)
[SI-LIST] Re: An SI engineer you should know - Powell, Doug
[SI-LIST] Re: Aspect Ratio - Venkat
[SI-LIST] Re: Aspect Ratio - Mcgrath, Christopher
[SI-LIST] Re: Aspect Ratio - Lee Ritchey
[SI-LIST] Re: Aspect Ratio - steve weir
[SI-LIST] Reliability Issue ATCA Mechanical Ejector engaging the Handle Switch - Salkow, Steven
[SI-LIST] RF PCB & Circuit Design - Parag Saxena