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Thread Index for si-list, 09-2005

[si-list] || [09-2005 Date Index] [09-2005 Thread Index]

  1. [SI-LIST] Re: 50 Ohm vs 75 ohm, Edi Fraiman
  2. [SI-LIST] Re: VME connector models, Mikhail Matusov
  3. [SI-LIST] Re: A doubt in PADS 2005, Anuj Goel
  4. [SI-LIST] AW: VME connector models, Witte, Markus
  5. [SI-LIST] Differential Z-One port, timoceous
  6. [SI-LIST] Re: Differential Z-One port, Ray Anderson
  7. [SI-LIST] Diff Z-One port, timoceous
  8. [SI-LIST] BUS TRANSLATION USING RESISTORS ONLY, MehranAbbasi
  9. [SI-LIST] Guidlines regarding the CE Certification for a Product, Adeel Malik
  10. [SI-LIST] Modeling and measurement of Connector, Matthias Bergmann
  11. [SI-LIST] dielectric conductance effect on rise time, Mark Burford
  12. [SI-LIST] EMI optimized CPLD/FPGA, atavou
  13. [SI-LIST] Re: EMI optimized CPLD/FPGA, Curt McNamara
  14. [SI-LIST] Contractor needed, Intel Oregon, Garrison, Gene
  15. [SI-LIST] DDR 2 Unbuffered DIMM - differential clock termination, John Ellis
  16. [SI-LIST] Re: Guidlines regarding the CE Certification for a Product, Curt McNamara
  17. [SI-LIST] Analog, "characterization" project, Kevin Pierpoint
  18. [SI-LIST] Signal Integrity opening at Enterasys Networks, Zanella, Fabrizio
  19. [SI-LIST] Effects of number of windings on ferrite core, Doug Smith
  20. [SI-LIST] Emissions radiated from Quartz Crystal, Adeel Malik
  21. [SI-LIST] Looking for IBIS model for any DDR2 SODIMM Module?, Unni Gangadharan
  22. [SI-LIST] Re: Looking for IBIS model for any DDR2 SODIMM Module?, Paglia, Frank M
  23. [SI-LIST] How to extract spice netlist from cadence BLD file?, Zhichao
  24. [SI-LIST] Stackup Suggestion for E1 transportor card, Suresh kumar
  25. [SI-LIST] New Semiconductor Technology, pritchard, jason
  26. [SI-LIST] September 13, 2005 IEEE-EMC Santa Clara Valley Chapter Social meeting, Ahmad Fallah
  27. [SI-LIST] Re: IBIS creation, Henrik G. Madsen
  28. [SI-LIST] Why should we tie AGND and DGND, nikitanivan
  29. [SI-LIST] 2006 EMC Symposium in Singapore, LI ERPING
  30. [SI-LIST] Re: Why should we tie AGND and DGND, Lee Ritchey
  31. [SI-LIST] when is a PE license required?, Robert Sefton
  32. [SI-LIST] Re: when is a PE license required?, Curt McNamara
  33. [SI-LIST] Analog and Digital grounds, Thomas McGonigle
  34. [SI-LIST] Re: Analog and Digital grounds, Dimiter Popoff
  35. [SI-LIST] About W-element formats, TerenceHsieh
  36. [SI-LIST] Re: About W-element formats, Tetsuhisa Mido
  37. [SI-LIST] Asian IBIS Summit Second Announcement, Bob Ross
  38. [SI-LIST] package design job, Jacobson, Karl
  39. [SI-LIST] Job Openings at Maxtor, Landrum, Chris
  40. [SI-LIST] can a bus hold circuit amplify crosstalk?, Peterson, James F (FL51)
  41. [SI-LIST] IBIS model for CY22393, an . le
  42. [SI-LIST] IBIS Modeling Cookbook for Version 4.0 available!, Mirmak, Michael
  43. [SI-LIST] Clock jitter, Kanakaraj
  44. [SI-LIST] Re: Clock jitter, rajneesh.raveendran
  45. [SI-LIST] Looking for few good Allegro men, Ludvik Kindl
  46. [SI-LIST] Poll- IBIS Creation, darshanmehta2k
  47. [SI-LIST] Flip Chip Solder Ball inductance, Bi Han
  48. [SI-LIST] Re: Flip Chip Solder Ball inductance, Aubrey_Sparkman
  49. [SI-LIST] R: Flip Chip Solder Ball inductance, Guasti Giovanni
  50. [SI-LIST] Recall: Re: Clock jitter, Sanderson, Brian
  51. [SI-LIST] IBIS model for Lattice FPGA XP failed icx parse., an . le
  52. [SI-LIST] PCB Trace Antenna, Boopathy J.
  53. [SI-LIST] Re: PCB Trace Antenna, Boopathy J.
  54. [SI-LIST] test, VSelvasuganthi
  55. [SI-LIST] Electrical length, Gaurav MATHUR
  56. [SI-LIST] XGMII interfaces, Vijay Hosamani
  57. [SI-LIST] Re: XGMII interfaces, Vijay Hosamani
  58. [SI-LIST] Partial Inductance, Albert Ruehli
  59. [SI-LIST] si post-process tool for sharing, Ke Wang
  60. [SI-LIST] What can we get from solid ground plane?, Bi Han
  61. [SI-LIST] How does HFSS model capacitors, KC
  62. [SI-LIST] Continue on the topic of partial inductance., Bi Han
  63. [SI-LIST] Re: si post-process tool for sharing, Vijay S CHACHRA
  64. [SI-LIST] Re: What can we get from solid ground plane?, Grasso, Charles
  65. [SI-LIST] regarding PCI-Express clocking scheme - dazzled & confused, Roy M
  66. [SI-LIST] LVDS Transmission Problem, Baris Duzgun
  67. [SI-LIST] R: LVDS Transmission Problem, Guasti Giovanni
  68. [SI-LIST] Re: LVDS Transmission Problem, steve weir
  69. [SI-LIST] Engineer and Technician openings at W.L. Gore & Associates, Inc., Jim R Broomall
  70. [SI-LIST] Re: R: LVDS Transmission Problem, Hassan O. Ali
  71. [SI-LIST] R: Re: R: LVDS Transmission Problem, Guasti Giovanni
  72. [SI-LIST] Re: R: Re: R: LVDS Transmission Problem, Hassan O. Ali
  73. [SI-LIST] questions for 2-layer PCB simulation, 吳亭瑩
  74. [SI-LIST] 回信： questions for 2-layer PCB simulation, Sogo Hsu
  75. [SI-LIST] entry level engineeing positions, bruce harvie
  76. [SI-LIST] Frequency dependent crosstalk coefficient, Fabrizio . Zanella
  77. [SI-LIST] Re: questions for 2-layer PCB simulation, Hargin, Bill
  78. [SI-LIST] Length matching of DDR-1 data lines - does it really have to be that tight?, Dimiter Popoff
  79. [SI-LIST] Re: Length matching of DDR-1 data lines - does it really have to be that tight?, Moran, Brian P
  80. [SI-LIST] Jitter Measurement Equipment and Techniques Net seminar., Vipul Badoni
  81. [SI-LIST] Re: Cref, Vref and Vmeas in IBIS file, Hargin, Bill




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