FreeLists / si-list / [SI-LIST] Re: EMI optimized CPLD/FPGA

["Curt McNamara" <CurtM@xxxxxxxxxxx>]

Antonis, it is the edge rate of signals which commonly causes EMI
problems
in complex designs. This is of course assuming other things like power
distribution and trace routing have been done properly in the design ...


CPLDs and FPGAs often have programmable slew rates, and if the signal
timing can tolerate the slower slew rate this can greatly help emissions
in many cases.=20

A related note is that choosing the slowest slew rate from the start
will help, and that as device families mature the geometries decrease
in size and the slew rates get faster. So what seems like an
innocuous die upgrade may in fact have major impacts on emissions.

Many companies establish regular re-testing or device change approval
strategies to manage these issues.

                                Curt

Curt McNamara. P.E.=20
Senior Electrical Engineer=20
Logic Product Development=20
411 Washington Ave. N Suite 101=20
Minneapolis, MN 55401=20
Tel 612-436-5178=20
Fax 612-672-0443=20
curtm@xxxxxxxxxxx=20
www.logicpd.com=20
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-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of steve weir
Sent: Tuesday, September 06, 2005 12:24 PM
To: atavou@xxxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: EMI optimized CPLD/FPGA


Antonis, no, but that really hasn't been a big problem.  FPGAs and CPLDs

are routinely used in products that meet European and North American EMC

standards.

Steve.
At 11:42 AM 9/6/2005 +0000, atavou@xxxxxxxxxxxxxxx wrote:

>Hi to all,
>
>We are currently developing a product that has to
>comply with military EMC standars. The board
>will include a CPLD/FPGA. Are there any product
>families that are EMI optimized?
>
>Regards,
>Antonis
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