Date Index for si-list, 09-2005

[si-list] || [09-2005 Date Index] [09-2005 Thread Index]

[SI-LIST] Re: 50 Ohm vs 75 ohm - Edi Fraiman
[SI-LIST] Re: VME connector models - Mikhail Matusov
[SI-LIST] Re: VME connector models - Fields, Brian
[SI-LIST] Re: A doubt in PADS 2005 - Anuj Goel
[SI-LIST] AW: VME connector models - Witte, Markus
[SI-LIST] Re: A doubt in PADS 2005 - Hargin, Bill
[SI-LIST] Mixed Signal Design Tools Workshop - Ege Engin
[SI-LIST] Differential Z-One port - timoceous
[SI-LIST] Re: Differential Z-One port - Ray Anderson
[SI-LIST] Re: Differential Z-One port - timoceous
[SI-LIST] Diff Z-One port - timoceous
[SI-LIST] Re: VME connector models - Syed Kamal Fasih
[SI-LIST] BUS TRANSLATION USING RESISTORS ONLY - MehranAbbasi
[SI-LIST] Re: BUS TRANSLATION USING RESISTORS ONLY - steve weir
[SI-LIST] Re: Differential Z-One port - Jinghua Huang
[SI-LIST] Guidlines regarding the CE Certification for a Product - Adeel Malik
[SI-LIST] Re: Guidlines regarding the CE Certification for a Product - Istvan Novak
[SI-LIST] Modeling and measurement of Connector - Matthias Bergmann
[SI-LIST] dielectric conductance effect on rise time - Mark Burford
[SI-LIST] EMI optimized CPLD/FPGA - atavou
[SI-LIST] Re: EMI optimized CPLD/FPGA - steve weir
[SI-LIST] Re: EMI optimized CPLD/FPGA - Curt McNamara
[SI-LIST] Contractor needed, Intel Oregon - Garrison, Gene
[SI-LIST] DDR 2 Unbuffered DIMM - differential clock termination - John Ellis
[SI-LIST] Re: Guidlines regarding the CE Certification for a Product - Curt McNamara
[SI-LIST] Analog, "characterization" project - Kevin Pierpoint
[SI-LIST] Signal Integrity opening at Enterasys Networks - Zanella, Fabrizio
[SI-LIST] Effects of number of windings on ferrite core - Doug Smith
[SI-LIST] Emissions radiated from Quartz Crystal - Adeel Malik
[SI-LIST] Looking for IBIS model for any DDR2 SODIMM Module? - Unni Gangadharan
[SI-LIST] Re: Looking for IBIS model for any DDR2 SODIMM Module? - Paglia, Frank M
[SI-LIST] Re: Looking for IBIS model for any DDR2 SODIMM Module? - Dunbar, Tony
[SI-LIST] How to extract spice netlist from cadence BLD file? - Zhichao
[SI-LIST] Stackup Suggestion for E1 transportor card - Suresh kumar
[SI-LIST] New Semiconductor Technology - pritchard, jason
[SI-LIST] Re: Stackup Suggestion for E1 transportor card - steve weir
[SI-LIST] September 13, 2005 IEEE-EMC Santa Clara Valley Chapter Social meeting - Ahmad Fallah
[SI-LIST] IBIS creation - Darshan Mehta
[SI-LIST] Re: IBIS creation - Henrik G. Madsen
[SI-LIST] Why should we tie AGND and DGND - nikitanivan
[SI-LIST] Re: IBIS creation - Darshan Mehta
[SI-LIST] 2006 EMC Symposium in Singapore - LI ERPING
[SI-LIST] Re: Why should we tie AGND and DGND - Mikhail Matusov
[SI-LIST] Re: Why should we tie AGND and DGND - Lee Ritchey
[SI-LIST] when is a PE license required? - Robert Sefton
[SI-LIST] Re: when is a PE license required? - Curt McNamara
[SI-LIST] Analog and Digital grounds - Thomas McGonigle
[SI-LIST] Re: Analog and Digital grounds - Stuart Brorson
[SI-LIST] Re: Analog and Digital grounds - Dimiter Popoff
[SI-LIST] About W-element formats - TerenceHsieh
[SI-LIST] Re: Analog and Digital grounds - Andrew Ingraham
[SI-LIST] Re: Analog and Digital grounds - POWELL, DOUG
[SI-LIST] Re: About W-element formats - Allan Wang
[SI-LIST] Mixed Signal Design Tools Workshop at Georgia Tech - Ege Engin
[SI-LIST] Re: About W-element formats - Tetsuhisa Mido
[SI-LIST] Asian IBIS Summit Second Announcement - Bob Ross
[SI-LIST] package design job - Jacobson, Karl
[SI-LIST] Job Openings at Maxtor - Landrum, Chris
[SI-LIST] can a bus hold circuit amplify crosstalk? - Peterson, James F (FL51)
[SI-LIST] IBIS - Darshan Mehta
[SI-LIST] IBIS model for CY22393 - an . le
[SI-LIST] IBIS Modeling Cookbook for Version 4.0 available! - Mirmak, Michael
[SI-LIST] Clock jitter - Kanakaraj
[SI-LIST] Re: Clock jitter - rajneesh.raveendran
[SI-LIST] Re: Clock jitter - eva_loney
[SI-LIST] Re: Clock jitter - Vinu Arumugham
[SI-LIST] Re: Clock jitter - Asbenson, Lyndell L
[SI-LIST] Re: Clock jitter - art_porter
[SI-LIST] Re: Clock jitter - bbolton
[SI-LIST] Looking for few good Allegro men - Ludvik Kindl
[SI-LIST] Poll- IBIS Creation - darshanmehta2k
[SI-LIST] Flip Chip Solder Ball inductance - Bi Han
[SI-LIST] Re: Flip Chip Solder Ball inductance - steve weir
[SI-LIST] Re： Re: Flip Chip Solder Ball inductance - Bi Han
[SI-LIST] Re: Flip Chip Solder Ball inductance - Aubrey_Sparkman
[SI-LIST] R: Flip Chip Solder Ball inductance - Guasti Giovanni
[SI-LIST] Re: Flip Chip Solder Ball inductance - Bi Han
[SI-LIST] Re: Clock jitter - Asbenson, Lyndell L
[SI-LIST] Re: Clock jitter - Sanderson, Brian
[SI-LIST] Recall: Re: Clock jitter - Sanderson, Brian
[SI-LIST] Re: Clock jitter - Sanderson, Brian
[SI-LIST] Re: Re： [SI-LIST] Re: Flip Chip Solder Ball i nd uctance - steve weir
[SI-LIST] Re: IBIS creation - Lynne D. Green
[SI-LIST] IBIS model for Lattice FPGA XP failed icx parse. - an . le
[SI-LIST] Re: IBIS model for Lattice FPGA XP failed icx parse. - Yafei Bi
[SI-LIST] DDR2 buffer model - Yuming Cheng
[SI-LIST] PCB Trace Antenna - Boopathy J.
[SI-LIST] Re: PCB Trace Antenna - Istvan Novak
[SI-LIST] Re: PCB Trace Antenna - Andrew Burnside
[SI-LIST] Re: PCB Trace Antenna - Boopathy J.
[SI-LIST] Re: PCB Trace Antenna - Istvan Novak
[SI-LIST] Re: PCB Trace Antenna - Zabinski, Patrick J.
[SI-LIST] Re: :PCB Trace Antenna - Virendra
[SI-LIST] Re: :PCB Trace Antenna - Andrew Burnside
[SI-LIST] PCB Trace Antenna - dav0
[SI-LIST] Re: :PCB Trace Antenna - Jian X. Zheng
[SI-LIST] test - VSelvasuganthi
[SI-LIST] OT: RoHS - Martin Euredjian
[SI-LIST] Re: Flip Chip Solder Ball inductance - Raymond Y. Chen
[SI-LIST] Electrical length - Gaurav MATHUR
[SI-LIST] XGMII interfaces - Vijay Hosamani
[SI-LIST] Re: XGMII interfaces - Vijay Hosamani
[SI-LIST] Re: Electrical length - Istvan Novak
[SI-LIST] Re: Flip Chip Solder Ball inductance - Bi Han
[SI-LIST] PCB Trace Antenna - Murez, Zachary J.
[SI-LIST] Re: Electrical length - ariazi
[SI-LIST] Partial Inductance - Albert Ruehli
[SI-LIST] Re: PCB Trace Antenna - Grasso, Charles
[SI-LIST] Re: Flip Chip Solder Ball inductance - steve weir
[SI-LIST] si post-process tool for sharing - Ke Wang
[SI-LIST] Re: Flip Chip Solder Ball inductance - Albert Ruehli
[SI-LIST] Re: Flip Chip Solder Ball inductance - steve weir
[SI-LIST] Re: Flip Chip Solder Ball inductance - Bi Han
[SI-LIST] What can we get from solid ground plane? - Bi Han
[SI-LIST] Re: What can we get from solid ground plane? - steve weir
[SI-LIST] Re: What can we get from solid ground plane? - Bi Han
[SI-LIST] How does HFSS model capacitors - KC
[SI-LIST] Continue on the topic of partial inductance. - Bi Han
[SI-LIST] Re: si post-process tool for sharing - Vijay S CHACHRA
[SI-LIST] Re: si post-process tool for sharing - steve weir
[SI-LIST] Re: What can we get from solid ground plane? - Albert Ruehli
[SI-LIST] Re: What can we get from solid ground plane? - Grasso, Charles
[SI-LIST] Re: What can we get from solid ground plane? - Grasso, Charles
[SI-LIST] regarding PCI-Express clocking scheme - dazzled & confused - Roy M
[SI-LIST] LVDS Transmission Problem - Baris Duzgun
[SI-LIST] R: LVDS Transmission Problem - Guasti Giovanni
[SI-LIST] Re: LVDS Transmission Problem - steve weir
[SI-LIST] Re: LVDS Transmission Problem - Scott McMorrow
[SI-LIST] Re： Re: What can we get from solid ground plane? - Bi Han
[SI-LIST] Re: regarding PCI-Express clocking scheme - dazzled & confused - Knut Georg Wiljugrein
[SI-LIST] Engineer and Technician openings at W.L. Gore & Associates, Inc. - Jim R Broomall
[SI-LIST] Re: R: LVDS Transmission Problem - Hassan O. Ali
[SI-LIST] R: Re: R: LVDS Transmission Problem - Guasti Giovanni
[SI-LIST] Re: R: Re: R: LVDS Transmission Problem - Hassan O. Ali
[SI-LIST] questions for 2-layer PCB simulation - 吳亭瑩
[SI-LIST] 回信： questions for 2-layer PCB simulation - Sogo Hsu
[SI-LIST] Re: regarding PCI-Express clocking scheme - dazzled & confused - Mike Brown
[SI-LIST] entry level engineeing positions - bruce harvie
[SI-LIST] Frequency dependent crosstalk coefficient - Fabrizio . Zanella
[SI-LIST] Re: questions for 2-layer PCB simulation - Hargin, Bill
[SI-LIST] Re: questions for 2-layer PCB simulation - steve weir
[SI-LIST] Re: questions for 2-layer PCB simulation - Ralf Bruening
[SI-LIST] Length matching of DDR-1 data lines - does it really have to be that tight? - Dimiter Popoff
[SI-LIST] Re: Length matching of DDR-1 data lines - does it really have to be that tight? - Dan Bostan
[SI-LIST] Re: Length matching of DDR-1 data lines - does it really have to be that tight? - Moran, Brian P
[SI-LIST] Re: questions for 2-layer PCB simulation - ???
[SI-LIST] Re: Length matching of DDR-1 data lines - does it really have to be that tight? - Shawn Arnold
[SI-LIST] Re: questions for 2-layer PCB simulation - steve weir
[SI-LIST] Re: Length matching of DDR-1 data lines - does it really have to be that tight? - Kenneth W. Egan
[SI-LIST] Jitter Measurement Equipment and Techniques Net seminar. - Vipul Badoni
[SI-LIST] Cref, Vref and Vmeas in IBIS file - Darshan Mehta
[SI-LIST] Re: Cref, Vref and Vmeas in IBIS file - Hargin, Bill
[SI-LIST] Re: Cref, Vref and Vmeas in IBIS file - Hargin, Bill