FreeLists / si-list / [SI-LIST] Re: Rocket I/O

[Jonathan Swift <jon_philip_swift@xxxxxxxxxxx>]

Hi Greg,

Just to clear up a few points, the RocketIO run length
is a limit set by the PLL that the SERDES uses for
CDR.  

As long as you are not breaking the 75
non-transitioning bit limit then yes you could recover
a clock embedded within a long stream of ones and
zeros. You could then use the data output of the
RocketIO into the FPGA architecture as a slow clock.

As to the 8b/10b others have mentioned, yes the Xilinx
RocketIO does have an encoder and decoder. However
this is by-passable and does not need to be used.
Using the 8b/10b will however guarantee that the run
length is never exceeded.

Hope this helps,

Jonathan

 --- "Inchauspe, Greg E" <greg.e.inchauspe@xxxxxxxx>
wrote: 
>               The data sheet for Rocket I/O specifies a minimum
> data
> rate of 620 Mbps. It also specifies a maximum of 75
> transition less data
> bits. If I transmit a pattern with 75 ones then 75
> zeros repeating NRZ
> at 620 Mbps, this is equivalent to a 4 MHz square
> wave. Does this mean
> the Rocket I/O can do clock and data recovery on a 4
> MHz square wave
> signal? 
>                  thanks,
>                  Greg
> 
> 
>
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