FreeLists / si-list / [SI-LIST] are the address lines overloaded that connect to two dimm of DDR chipset ?

[meng.yubao@xxxxxxxxxx]

Dear all:
       I have a design with two dimms of DDR RAM, I have one address bus 
to connect two dimms with their drivers of FPGA. in the design i am afraid 
that the address drivers are overloaded, is my worry unnecessary? anyone's 
advice will be appreciated!

best regards

mengyb

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