FreeLists / si-list / [SI-LIST] Decoupling for PLL (continued)

[Zhangkun <zhang_kun@xxxxxxxxxx>]

Dear all
Recently, I have done some measurement. It is found that when the 
bead(inductor) is used, the power ground noise at 333KHz from VRM is larger. 
There is some noise near the clock frequency points.

For example, the output clock of PLL is 50MHz. At 50.333MHz and 49.667MHz, 
there is noise, which is in proportion to the noise at 333KHz. Maybe the PLL 
modulates the noise of VRM into the output clock.

Is there any SPICE model for PLL?

Best Regards

Zhangkun
2004.9.3


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