FreeLists / si-list / [SI-LIST] ground in RF chip

["Bi, Han" <han.bi@xxxxxxxxx>]

What¡¯s the question?
In high speed or RF integrated circuit design, sometimes we need to use very 
long transmission lines in the chip, such as distributed amplifier. What we 
need to in the very first step is to model the transmission line.

For example, we are planning to use CPS(coplanar stripe line) as the 
compensation element in the circuit. 

 

Issue?

The difficulty was that the ground metal trace in the CPS line will be 
difficult to deal with. We have made experiment to extract the RLGC model of 
the CPS in two ways. 

 

First, we just made the ground trace as ideal ground. 

Second, we model the ground trace as lossy signal line whose two terminals was 
grounded. 

 

The simulation results showed that the loss of the metal ground will make the 
crosstalk and loss of transmissions greater. This lead to a interesting way to 
improve the performance of CPS in the chip. 

We just want to give a better grounding to the CPS¡¯s ground trace, we use 
stacked vias at the outside of ground trace to connect top metal to the 
substrate.

 

Do you think that helpful? 

 

The answer may lead to the questioning where is the acceptable ground in RF 
chip?

 

Thanks!

Yours sincerely,

Bi Han 

DE/WPS/FPG/Intel Corporation 

Phone: 86-(21)-50481818-32283 

iNet: 8-753-2283 

 

 


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