Date Index for si-list, 09-2003

[si-list] || [09-2003 Date Index] [09-2003 Thread Index]

[SI-LIST] RF ground in RF chip - Bi Han
[SI-LIST] Re: Model of Capacitors - Bart Bouma
[SI-LIST] Re: Model of Capacitors - Geoff Stokes
[SI-LIST] Re: Model of Capacitors - Bart Bouma
[SI-LIST] HSpice recursive convolution implementation - Radoslaw Piesiewicz
[SI-LIST] HSpice implementation of recursive convolution - Radoslaw Piesiewicz
[SI-LIST] Re: RF ground in RF chip - Swanson, Dan
[SI-LIST] Re: Model of Capacitors - fred
[SI-LIST] ground in RF chip - Bi, Han
[SI-LIST] testing LVPECL signal with 50ohm system - Dan.Zhu
[SI-LIST] Re: HSpice implementation of recursive convolution - Raymond Anderson
[SI-LIST] Re: RF ground in RF chip - Bi Han
[SI-LIST] Re: HSpice implementation of recursive convolution - Radoslaw Piesiewicz
[SI-LIST] Re: testing LVPECL signal with 50ohm system - Bob McNamara
[SI-LIST] Re: RF ground in RF chip - D G
[SI-LIST] Re: HSpice implementation of recursive convolution - Ray Anderson
[SI-LIST] Re: HSpice implementation of recursive convolution - Jon Powell
[SI-LIST] relation b/w impedance and SI - karan bagga
[SI-LIST] Re: HSpice implementation of recursive convolution - Clewell, Craig
[SI-LIST] Interface for FLat panel Displays - Nitin Sood
[SI-LIST] Re: testing LVPECL signal with 50ohm system - Michael Poimboeuf
[SI-LIST] IEEE CPMT Society Phoenix Chapter - 9/22/03 meeting announcement - Sam Karikalan
[SI-LIST] GND is perfect conductor? - Loyer, Jeff
[SI-LIST] Re: GND is perfect conductor? - Zabinski, Patrick J.
[SI-LIST] Re: GND is perfect conductor? - McCoy, Bart O.
[SI-LIST] Inductance of wire section - Stuart Brorson
[SI-LIST] FW: Inductance of wire section - McCoy, Bart O.
[SI-LIST] Re: Job Opportunities - jeremy hillcrest
[SI-LIST] Re: FW: Inductance of wire section - Ken Cantrell
[SI-LIST] Re: GND is perfect conductor? - D G
[SI-LIST] Re: FW: Inductance of wire section - McCoy, Bart O.
[SI-LIST] Re: Inductance of wire section - Charles Grasso
[SI-LIST] Fwd: Re: relation b/w impedance and SI - karan bagga
[SI-LIST] (EMI)spread spectrum clocking - karan bagga
[SI-LIST] Re: FW: Inductance of wire section - Geoff Stokes
[SI-LIST] Re: (EMI)spread spectrum clocking - Istvan NOVAK
[SI-LIST] Re: GMII & RGMII timing analysis - msmurthy murthy
[SI-LIST] Re: FW: Inductance of wire section - Ken Cantrell
[SI-LIST] Re: Inductance of wire section - Stuart Brorson
[SI-LIST] Parasitic resonance in DC-DC converters - KR, Chandrashekhar
[SI-LIST] Re: Inductance of wire section - Kim Flint
[SI-LIST] Re: Inductance of wire section - bpanos
[SI-LIST] Re: Inductance of wire section - Mark Potter
[SI-LIST] Is this kind of software available in the market? - haowang
[SI-LIST] FastHenry .external and .equiv - Andy Kuo
[SI-LIST] Re: (EMI)spread spectrum clocking - bkemp
[SI-LIST] Re: (EMI)spread spectrum clocking - Michael Poimboeuf
[SI-LIST] =?big5?q?=A6^=ABH=A1G?= Is this kind of softwareavailable in the market? - Feng F. Zhang
[SI-LIST] Re: (EMI)spread spectrum clocking - Salkow, Steven
[SI-LIST] Re: (EMI)spread spectrum clocking - karan bagga
[SI-LIST] Impact of finite and irregular ground planes on stripline bandwidth - Walter Kreiger
[SI-LIST] Re: Inductance of wire section - Kim Flint
[SI-LIST] transmission line characteristic impedance (Zo) value - pawankalyan_india
[SI-LIST] Re: Fwd: Re: relation b/w impedance and SI - Ingraham, Andrew
[SI-LIST] Re: (EMI)spread spectrum clocking - Ingraham, Andrew
[SI-LIST] Re: GND is perfect conductor? - Ingraham, Andrew
[SI-LIST] trying to get in touch with the listed people - Istvan NOVAK
[SI-LIST] TEM approximation - Swamy Dhoss
[SI-LIST] AW: FastHenry .external and .equiv - Neibig Uwe (GS/EDK) *
[SI-LIST] Re: Is this kind of software available in the market? - Swanson, Dan
[SI-LIST] Re: Is this kind of software available in the market? - Clewell, Craig
[SI-LIST] Re: Is this kind of software available in the market? - c deibele
[SI-LIST] Reference Plane - Zhangkun
[SI-LIST] Re: Is this kind of software available in the market? - Ekkehard Miersch
[SI-LIST] Re: Is this kind of software available in the market? - Hassan O. Ali
[SI-LIST] Re: Is this kind of software available in the market? - Hassan O. Ali
[SI-LIST] Re: Reference Plane - Lee Ritchey
[SI-LIST] Re: Is this kind of software available in the market? - Jian-X. Zheng
[SI-LIST] Re: Reference Plane - Loyer, Jeff
[SI-LIST] GND is perfect conductor? - Lynne Green
[SI-LIST] Re: Reference Plane - Lee Ritchey
[SI-LIST] Re: Reference Plane - Loyer, Jeff
[SI-LIST] Return Path Usage - Moeller, Merrick
[SI-LIST] Re: Return Path Usage - Moeller, Merrick
[SI-LIST] Re: Reference Plane - Lee Ritchey
[SI-LIST] Re: Is this kind of software available in the market? - Dima Smolyansky
[SI-LIST] Re: si-list Digest V3 #259 - Thomas Beneken
[SI-LIST] Antenna's - G S
[SI-LIST] Diff. Bal. to Unbal. Transition - Bradley S Henson
[SI-LIST] Where Can I Get FastHenry and FastCap - AmateurND
[SI-LIST] Re: Where Can I Get FastHenry and FastCap - Jeff Jones
[SI-LIST] Re: Where Can I Get FastHenry and FastCap - Chan, Michael (Eng Hou)
[SI-LIST] Re: Antenna's - sivi.cla@xxxxxxxxx
[SI-LIST] RMCEMC September Meeting Announcement - Charles Grasso
[SI-LIST] RMCEMC Aug Meeting downloads and other offerings - Charles Grasso
[SI-LIST] Significant error in signal measurements - Doug Smith
[SI-LIST] Re: Antenna's - Steve Rogers
[SI-LIST] Re: GND is perfect conductor? - Jack
[SI-LIST] regarding 1394 firewire - K. Sankar
[SI-LIST] Re: Diff. Bal. to Unbal. Transition - Scott McMorrow
[SI-LIST] Re: GND is perfect conductor? - Ingraham, Andrew
[SI-LIST] Re: regarding 1394 firewire - Jon Powell
[SI-LIST] Re: Diff. Bal. to Unbal. Transition - Loyer, Jeff
[SI-LIST] Antennas (contd) - G S
[SI-LIST] Re: Diff. Bal. to Unbal. Transition - Vinu Arumugham
[SI-LIST] Re: Diff. Bal. to Unbal. Transition - Loyer, Jeff
[SI-LIST] 6 Layer Stack-up - Vishram Pandit
[SI-LIST] Re: 6 Layer Stack-up - Hassan O. Ali
[SI-LIST] Re: 6 Layer Stack-up - Ravinder . Ajmani
[SI-LIST] Re: 6 Layer Stack-up - Nguyen, Mike
[SI-LIST] Re: 6 Layer Stack-up - Ravinder . Ajmani
[SI-LIST] Re: 6 Layer Stack-up - Vishram Pandit
[SI-LIST] RMCEMC August Presentation Download available - Charles Grasso
[SI-LIST] how can I use the R params in EBD file path Description? - cat
[SI-LIST] sorry to bother,dont mind my former mail "how can I use the R params in EBD file path Description?" - cat
[SI-LIST] Re: 6 Layer Stack-up - Sudheer B S
[SI-LIST] Re: A question about data mask in SDRAM/DDR - keksoonpoh
[SI-LIST] SDRAM connection - Adeel Malik
[SI-LIST] Change in access to si-list files on Yahoogroups site - Ray Anderson
[SI-LIST] Re: SDRAM connection - Mehrdad Salami
[SI-LIST] Re: SDRAM connection - Eric Deys
[SI-LIST] Length matching of differential pair - #CHUANG KENG HUA#
[SI-LIST] Re: Antennas (contd) - Kevin Skey
[SI-LIST] Re: Antennas (contd) - Christopher Jakubiec
[SI-LIST] Call for participation deadline extended - Andy Shaughnessy
[SI-LIST] Re: 6 Layer Stack-up - steve weir
[SI-LIST] Re: 6 Layer Stack-up - bdempsey85
[SI-LIST] Re: 6 Layer Stack-up - steve weir
[SI-LIST] Re: 6 Layer Stack-up - Lee Ritchey
[SI-LIST] Re: 6 Layer Stack-up - Lee Ritchey
[SI-LIST] Re: 6 Layer Stack-up - Chris Cheng
[SI-LIST] Non-negative off diagonal capacitive matrix - Andy Kuo
[SI-LIST] Re: 6 Layer Stack-up - Ravinder . Ajmani
[SI-LIST] Re: 6 Layer Stack-up - Chris Cheng
[SI-LIST] lumped vs distributed - karan bagga
[SI-LIST] Re: 6 Layer Stack-up - john . matthews
[SI-LIST] Re: 6 Layer Stack-up - Brent DeWitt
[SI-LIST] simulate isfet model using Hspice - Rozina Abd. Rani
[SI-LIST] 1394 differential traces - Maheshwari.P
[SI-LIST] help in mentorgraphics librarian - rishikesh pawar
[SI-LIST] peeling algorithm - praveenayala pend
[SI-LIST] Interfacing DDR 400 DRAM Chips to Xilinx Virtex II FPGA. - Siva kumar
[SI-LIST] Re: Interfacing DDR 400 DRAM Chips to Xilinx Virtex II FPGA. - steve weir
[SI-LIST] DDR SDRAM layout considerations - Ken Hayden
[SI-LIST] Re: lumped vs distributed - Dima Smolyansky
[SI-LIST] Re: 1394 differential traces - Mark Millison
[SI-LIST] Thanks for your responses - Re: Re: Antennas (contd) - G S
[SI-LIST] RMS Phase Error and BER - Himanshu Arora
[SI-LIST] Re: DDR SDRAM layout considerations - Bob McNamara
[SI-LIST] Re: RMS Phase Error and BER - Mike Li
[SI-LIST] Re: 6 Layer Stack-up - Chris Cheng
[SI-LIST] Re: DDR SDRAM layout considerations - Ravinder . Ajmani
[SI-LIST] Job search. - Gurumurthy, Radhika
[SI-LIST] Re: DDR SDRAM layout considerations - Prakash Chauhan
[SI-LIST] Re: simulate isfet model using Hspice - Lynne Green
[SI-LIST] Re: lumped vs distributed - Lynne Green
[SI-LIST] Re: 1394 differential traces - Grasso, Charles
[SI-LIST] Re: DDR SDRAM layout considerations - john lipsius
[SI-LIST] Re: 6 Layer Stack-up - John Matthews
[SI-LIST] Re: 6 Layer Stack-up (TANSTAAFL) - Scott McMorrow
[SI-LIST] Thermal resistance values - Nico Fleurinck
[SI-LIST] Re: Thermal resistance values - Fred U. Rosenberger
[SI-LIST] Re: Thermal resistance values - Steve Rogers
[SI-LIST] Re: Thermal resistance values - Pat Diao
[SI-LIST] Re: 6 Layer Stack-up (TANSTAAFL) - Tegan Campbell
[SI-LIST] Re: 6 Layer Stack-up (TANSTAAFL) - Scott McMorrow
[SI-LIST] Re: 6 Layer Stack-up (TANSTAAFL) - Chris Cheng
[SI-LIST] Re: 6 Layer Stack-up (TANSTAAFL) - Chris Cheng
[SI-LIST] Re: DDR SDRAM layout considerations - Tadashi Arai
[SI-LIST] split plane - Santhosh E P
[SI-LIST] impedance relation with frequency... - karan bagga
[SI-LIST] Re: split plane - steve weir
[SI-LIST] Re: SDRAM connection - Adeel Malik
[SI-LIST] Signal Integrity opportunity-Austin Texas - Alan Butz
[SI-LIST] Dell Servers Signal Integrity Group has an immediateopening.... - Michael_Greim
[SI-LIST] Re: impedance relation with frequency... - Jon Powell
[SI-LIST] Re: split plane - Drew
[SI-LIST] AGTL+ transceiver? - Joyce, Paul
[SI-LIST] Re: impedance relation with frequency... - andrew . c . byers
[SI-LIST] Invitation to HYTEK & Future Electronics 'Future Faire', a program By Engineers For Engineers (BEFE) - Patriack O'Shea
[SI-LIST] SGMII material - Shiming Wang
[SI-LIST] how to improve bus speed in board - ZHIYONG_ZHANG
[SI-LIST] Re: TEM approximation - Dima Smolyansky
[SI-LIST] Manuals for Fastcap and FastHenry - AmateurND
[SI-LIST] CPCI backplane diode termination - Nico Fleurinck
[SI-LIST] Fabricating an PCB with an odd layer count - Chris McGrath
[SI-LIST] Re: Manuals for Fastcap and FastHenry - Raj Raghuram
[SI-LIST] Decoupling model - antonioccd
[SI-LIST] Re: Manuals for Fastcap and FastHenry - Abe Riazi
[SI-LIST] Electrical Specifications for OC-12 - Mark Flanigan
[SI-LIST] Article on Bounce - Lynne Green
[SI-LIST] Re: TEM approximation - Chris Cheng
[SI-LIST] maybe some oversight in ebd defination? - cat
[SI-LIST] Re: TEM approximation - Steve Corey
[SI-LIST] Re: TEM approximation - jizheng
[SI-LIST] LVDS cable - Vinay G
[SI-LIST] Re: LVDS cable - Hofmann, Mark
[SI-LIST] Re: TEM approximation - Chris Cheng
[SI-LIST] simulating AC coupling with HSPICE - Gil Gafni
[SI-LIST] Re: LVDS cable - Michael Poimboeuf
[SI-LIST] Re: simulating AC coupling with HSPICE - Kim Helliwell
[SI-LIST] Re: simulating AC coupling with HSPICE - Duane Takahashi
[SI-LIST] Re: TEM approximation - Jon Powell
[SI-LIST] Re: TEM approximation - Chris Cheng
[SI-LIST] Impact of gap on stripline trace - Frank Dunlap
[SI-LIST] Re: simulating AC coupling with HSPICE - Mellitz, Richard
[SI-LIST] PWL generator for SPICE upgraded - Beal, Weston
[SI-LIST] Re: TEM approximation - Steve Corey
[SI-LIST] Re: simulating AC coupling with HSPICE - Ingraham, Andrew
[SI-LIST] File access on Yahoo Groups denied - MikonCons
[SI-LIST] Re : maybe something wrong in ebd defination? - cat
[SI-LIST] Re: a problem about PLL bypass - Bi Han
[SI-LIST] SYSTEM CONFIG REQD - sunil raj
[SI-LIST] Re: Impact of gap on stripline trace - Michael Khusid
[SI-LIST] Re: a problem about PLL bypass - Ed Miguel
[SI-LIST] Re: Re : maybe something wrong in ebd definition? - Jon Powell
[SI-LIST] Re: Re : maybe something wrong in ebd defination? - Beal, Weston
[SI-LIST] Re: Re : maybe something wrong in ebd definition? - Scott McMorrow
[SI-LIST] [Fwd: [IBIS-Users] static/dynamic overshoot/undershoot definition] - Perry Qu
[SI-LIST] Re: [Fwd: [IBIS-Users] static/dynamic overshoot/undershoot definition] - Beal, Weston
[SI-LIST] Re: Re : maybe something wrong in ebd definition? - Muranyi, Arpad
[SI-LIST] Decoupling capacitor and oscillations - nvasrikanth
[SI-LIST] Bus Routing - Vikas Chandra Rao
[SI-LIST] Re: [Fwd: [IBIS-Users] static/dynamic overshoot/undershoot definition] - Perry Qu
[SI-LIST] Re: SYSTEM CONFIG REQD - Kai Keskinen
[SI-LIST] Re: Antennas (contd) - Frank Dunlap
[SI-LIST] Re: Decoupling capacitor and oscillations - Bi Han
[SI-LIST] de-embedding of mems - Kaustubh Bhate
[SI-LIST] Re: de-embedding of mems - Swanson, Dan
[SI-LIST] Re: TEM approximation - Zhou, Xingling (Mick)
[SI-LIST] high speed connector - jan gillis
[SI-LIST] Re: de-embedding of mems - Kaustubh Bhate
[SI-LIST] Re: TEM approximation - Steve Corey
[SI-LIST] Re: Re : maybe something wrong in ebd defination? - Bob Ross
[SI-LIST] Re: TEM Approximation - norhan
[SI-LIST] Loss Tangent (HELP!) - Steve Rogers
[SI-LIST] trade-off between using vias and longer trace length - Ethan Tsai
[SI-LIST] Re: TEM Approximation - Steve Corey
[SI-LIST] Re: de-embedding of mems - package_char
(no subject) - chandthana
[SI-LIST] Re: (no subject) - Tom Dagostino
[SI-LIST] Re: impedance relation with frequency... - Loyer, Jeff
[SI-LIST] Re: impedance relation with frequency... - Scott McMorrow
[SI-LIST] Re: impedance relation with frequency... - andrew . c . byers
[SI-LIST] Re: Impact of gap on stripline trace - Loyer, Jeff
[SI-LIST] Re: impedance relation with frequency... - Loyer, Jeff
[SI-LIST] Re: impedance relation with frequency... - Martyn Gaudion
[SI-LIST] Voids in Solder Joints - Gupta, Deepali
[SI-LIST] Re: Impact of gap on stripline trace - Loyer, Jeff
[SI-LIST] Re: Impact of gap on stripline trace - Tom Dagostino
[SI-LIST] Re: Voids in Solder Joints - Salkow, Steven
[SI-LIST] trade-off between using vias and longer trace length - cjt
[SI-LIST] Re: de-embedding of mems - gh c
[SI-LIST] Re: TEM Approximation - norhan
[SI-LIST] differential pairs crosstalk effect - =?big5?b?IkhvLCBKZWZmICim86xGvrEgSUVDMSki?=
[SI-LIST] Re: differential pairs crosstalk effect - Istvan NOVAK
[SI-LIST] Re: differential pairs crosstalk effect - Zhangkun
[SI-LIST] lvds TL - Claudio Siviero
[SI-LIST] Re: TEM Approximation - Swanson, Dan
[SI-LIST] Re: Voids in Solder Joints - Dimiter Popoff
[SI-LIST] Re: impedance relation with frequency... - Jon Powell
[SI-LIST] Re: impedance relation with frequency... - Loyer, Jeff
[SI-LIST] Re: impedance relation with frequency... - Jon Powell
[SI-LIST] Re: impedance relation with frequency... - Martyn Gaudion
[SI-LIST] Re: Impact of gap on stripline trace - bdempsey85
[SI-LIST] UltraCAD's upgraded freeware transmission line impedance calculator - Doug Brooks
[SI-LIST] HSPICE trainings - Eric Blomberg - Sun Microsystems
[SI-LIST] Re: HSPICE trainings - Tracy Barclay
[SI-LIST] Re: impedance relation with frequency... - Salkow, Steven
[SI-LIST] Fr 4 Er variation - Scott McMorrow
[SI-LIST] Guard traces for differetial pairs - Tonglong Zhang
[SI-LIST] High Impedance Traces are prone to Radio Frequency Interference - Lim Guan Choon
[SI-LIST] Re: High Impedance Traces are prone to Radio Frequency Interference - Steve Rogers
[SI-LIST] HyperLynx vs Hspice - Naveen Reddy
[SI-LIST] HyperLynx vs Hspice - Naveen Reddy
[SI-LIST] Re: Impact of gap on stripline trace - Frank Dunlap
[SI-LIST] Re: Impact of gap on stripline trace - Tom Dagostino
[SI-LIST] Re: Hyperlynx vs. Hspice - Jon Powell
[SI-LIST] Re: Hyperlynx vs. Hspice - Fred Balistreri
[SI-LIST] Re: Hyperlynx vs. Hspice - Stephen Zinck
[SI-LIST] Re: Hyperlynx vs. Hspice - Chris Cheng
[SI-LIST] Re: Hyperlynx vs. Hspice - Jon Powell
[SI-LIST] Re: Hyperlynx vs. Hspice - Duane Takahashi
[SI-LIST] Re: Guard traces for differetial pairs - Lee Ritchey
[SI-LIST] Re: HyperLynx vs Hspice - Hargin, Bill
[SI-LIST] Re: HyperLynx vs Hspice - Douglas Burns
[SI-LIST] Re: Guard traces for differetial pairs - Scott McMorrow
[SI-LIST] usage of [Model Spec] Keyword - lokprakash
[SI-LIST] Re: Guard traces for differetial pairs - MikonCons
[SI-LIST] =?big5?q?=A6^=ABH=A1G?= Re: Guard traces for differetialpairs - Sogo Hsu
[SI-LIST] Re: Guard traces for differetial pairs - =?big5?q?sghsu55?=
[SI-LIST] Re: Guard traces for differetial pairs - Istvan NOVAK
[SI-LIST] HSPICE - Deciding Max. route length - Siva Krishna
[SI-LIST] eye diagram - karan bagga
[SI-LIST] Regarding DFM - G.Ganesh Kumar
[SI-LIST] Signal Integrity-Simplified, new book - Eric Bogatin
[SI-LIST] Re: HyperLynx vs Hspice - Muranyi, Arpad
[SI-LIST] Re: eye diagram - San Miguel, Shane
[SI-LIST] Re: Guard traces for differential pairs - Duane Takahashi
[SI-LIST] Clock phase Margin - nasir
[SI-LIST] Re: usage of [Model Spec] Keyword - Mirmak, Michael
[SI-LIST] Hspice Toolbox for Matlab - Raymond Anderson
[SI-LIST] (no subject) - Rudy Q
[SI-LIST] Re: Guard traces for differential pairs - Chris Cheng
[SI-LIST] Re: eye diagram - art_porter
[SI-LIST] Re: Guard traces for differential pairs - Damon Bowser
[SI-LIST] FW: eye diagram - jeff_latourrette
[SI-LIST] Re: HyperLynx vs Hspice - Lynne Green
[SI-LIST] Re: Guard traces for differential pairs - Duane Takahashi
[SI-LIST] Re: Guard traces for differential pairs - Scott McMorrow
[SI-LIST] USB 2.0 testing - Kupper, Ingo
[SI-LIST] Re: Guard traces for differential pairs - Grasso, Charles
[SI-LIST] power consuming of OSC - Zhangkun
[SI-LIST] RJ45 interfacing with RS232 - venu
[SI-LIST] Re: RJ45 interfacing with RS232 - steve weir
[SI-LIST] Split power Plane support for Hyperlynx - Suresh.K
[SI-LIST] rf measurements - Kaustubh Bhate
[SI-LIST] Terminal Emulator supporting 406.8 kbps - Adeel Malik
[SI-LIST] Books on Package Design. - Rahul R
[SI-LIST] Re: RJ45 interfacing with RS232 - Bill Reams
[SI-LIST] Hardware Design guru - FYI - David Cohen
[SI-LIST] Re: HyperLynx vs Hspice - Mike LaBonte
[SI-LIST] Re: Books on Package Design. - Chris Schmolze
[SI-LIST] Simulating Wiring Harnesses and Cables. - Moeller, Merrick
[SI-LIST] Re: Guard traces for differential pairs - Duane Takahashi
[SI-LIST] Anyone doing 802.3ab 1000BT gigabit ethernet SI testing? - Michael Poimboeuf
[SI-LIST] Hspice net? - AZ
[SI-LIST] Re: Hardware Design guru - FYI - Dr. Edward P. Sayre
[SI-LIST] Fwd: Comments, good bye to wrinkles--- (from Nita Ho) - Dr. Edward P. Sayre
[SI-LIST] Fwd: Comments, good bye to wrinkles--- (from Nita Ho) - Dr. Edward P. Sayre
[SI-LIST] Re: Guard traces for differential pairs - Chris Cheng
[SI-LIST] Re: Hspice net? - Stuart Brorson
[SI-LIST] Re: Hspice net? - Jon Powell
[SI-LIST] Re: Split power Plane support for Hyperlynx - Angulo, John
[SI-LIST] Webinar on Differential IBIS Models - Lynne Green
[SI-LIST] Re: [IBIS] Webinar on Differential IBIS Models - Muranyi, Arpad
[SI-LIST] Re: Hspice net? - Mike Mayer