FreeLists / si-list / [SI-LIST] Re: about 'flat region'

["Perry Qu" <Perry.Qu@xxxxxxxxxxx>]

Zheng:

I suggest that you check your receiver IC packaging. If it's a fairly big
BGA with large parasitic L/Cs, what you measured at the receiver pin may
not what the I/O cells on the die sees. For a fast rise time signal,
those IC packaging traces/wire bonds act as a transmission line, thus
effectively you are probeing in the middle of a transmission and shelf is
expected on rising/falling edge.

Suggest you do the following simple test: remove your IC altogether and
put a lump cap (e.g., 10pF) at the receiver pin. Measure the signal again
and see whether you still see that shelf.

I had a few cases where we see shelf on edges when probed at receiver
pin. By properly modelling of IC packaging, I get good correlation with
measurement. Also,  the simulation shows that the signal at die looks ok
(no shelf but with some overshoot). In such case, you need simulation to
back up hardware verfication since it's not quite possible to probe the
signal at die level.

Regards

Perry

qzheng wrote:

> Hello si-list,
>
>    Always we can observe  'flat region or shelf ' at the rising or
>
>    falling edge , and this may produce some error in digital circuits
>
>    , so where can i find some literature about this problem ??
>
>
>    thanks in advance
>
> --
> Best regards,
>  qzheng                          mailto:qzheng@xxxxxxxxxxxxxxxx
>
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--
Perry Qu

Product Integrity         |      600 March Road
Alcatel Canada            |      Ottawa, ON K2K 2E6, Canada

DID: (613) 7846720        |      FAX: (613) 5993642


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