FreeLists / si-list / [SI-LIST] about 'flat region'

[qzheng <qzheng@xxxxxxxxxxxxxxxx>]

Hello si-list,

   Always we can observe  'flat region or shelf ' at the rising or

   falling edge , and this may produce some error in digital circuits

   , so where can i find some literature about this problem ??

   
   thanks in advance


-- 
Best regards,
 qzheng                          mailto:qzheng@xxxxxxxxxxxxxxxx

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