FreeLists / si-list / [SI-LIST] Re: Self Inductance and TDR measurements

[Neeraj Pendse <cnepsc@xxxxxxxxxxxxxxx>]

Anil:

I will write a couple of thoughts to what Patrick has pointed out:

When you are looking at a TPA simulation matrix, you are probably looking at
PARTIAL inductance of the elements, i.e inductance with no specific return
path. I think matrix reduction allows you to get loop inductance also - but
I do not use TPA and I am not sure how good a loop inductance number will it
spit out when there are planes present.

When doing your TDR measurement, if you create the currents in such a way
that they mimick the currents flowing in the application or at least mimick
the current that the your simulation tool will put on the conductor. The
whole idea is to get the current distribution right ... or else you can not
compare. This you do by selecting the right solder balls to connect to
ground, rather than "all but those under measurment".   Leave the solder
balls that are heavily coupled to the trace under test unconnected to
ground. That way the effects of their mutuals will not corrupt your
measurement. If you are looking for loop inductance through a plane, then
connect only the solderballs going to that plane to TDR reference ground.
Internally, you will have to bond the bond finger of the trace to the ring.

Anyway, let me know if you have any further questions.
Regards,

- Neeraj Pendse

National Semiconductor Corporation
2900 Semiconductor Drive, Mail Stop 19-100
Santa Clara, California 95051
http://www.national.com/ NYSE: NSM


"Zabinski, Patrick J." wrote:

>
> > a) Pat has confirmed the method I was using to calculate the self
> > capacitance. However for inductance I have just been using
> > L11 as the self
> > inductance. Is this correct?
> >
>
> Yes.  The inductance matrix produced by most EM cross section
> simulation tools is just that; inductance, and you can read the
> values directly (both on- and off-diagonal).
>
> > b) However I am still puzzled over which # to use to compare with TDR
> > measurements.
> > The TDR measurements we do use a fixture from ALTAIR
> > microwave which has a
> > Cu sheet on which the package balls sit and grounds all other
> > pins in the
> > package except for the pin of interest.
> >
>
> Capacitance is easier (at least for me) to visualize, because in
> TEM mode, parallel plate capacitance can be directly calculated
> based on the two elements you're trying to calculate the
> capacitance between.
>
> For inductance, it gets a bit more difficult, in that inductance is
> for the "entire loop".  For example, inductance of a wire
> is incomplete if you do not include the return inductance.
>
> It is sometimes difficult (impossible?) to directly compare
> the inductance produced by a simulation tool to something
> you measure in the lab.
>
> In the situation you describe (if I'm reading in between the
> lines correctly), you are trying to measure the inductance of
> a single trace with all other traces grounded.  The problem
> is (typically in most BGA designs) that the grounded traces
> have mutual coupling to the line of interest, so their presence
> effects your measurement.
>
> Also in your case, it might be that the referenced ground plane
> in the simulation is not necessarily the return path
> in your measurement, which will throw things off.
>
> In addition, if the trace you're measuring exits the BGA
> at an appreciable distance from the ground-plane ball(s),
> the separation can increase the effective inductance.
>
> In short, I've have pretty good success in correlating
> capacitance, but inductance is a real bugger of a parameter
> to correlate without taking a few (sometimes many) extra
> steps to make sure you are truly correlating the same
> parameter.
>
> >  I have not got a good answer yet as to which number in the simulation
> > matrix I should compare the TDR meas. to.
> >
>
> Here are a few to keep you busy:
>
> TITLE   Validity of Mutual Inductor Model for Electromagnetic Coupling
> Between V
> ias in Integrated-Circuit Packages and Printed Circuit Boards
> AUTHOR  Jin Zhao and Jiayuan Fang
> SOURCE  1998 ECTC Conference, Seattle, WA
> DATE    May 25-28, 1998
> PAGES   na
>
> TITLE   Capacitance, Inductance, and Crosstalk Analysis
> AUTHOR  Charles S. Walker
> SOURCE  Artech House, Boston
> ISBN    0-89006-392-3
> DATE    1990
>
> TITLE   Extraction of Coupled SPICE Models for Packages and Interconnects
> AUTHOR  Scott Diamond and Bo Janko
> SOURCE  Proceedings of IEEE International Test Conference
> DATE    October 1993
> PAGES   Paper 20.1
>
> TITLE   Guideline for Measurement of Electronic Package Inductance and
> Capacitan
> ce Model Parameters
> AUTHOR  na
> SOURCE  EIA Standard JEP123
> DATE    October 1995
> PAGES   1-20
>
> TITLE   Loop Areas - Close 'Em Tight
> AUTHOR  D. Brooks
> SOURCE  Printed Circuit Design Magazine
> DATE    January 1999
>
> TITLE   Measuring Package and Interconnect Model Parameters Using
> Distributed Im
> pedance
> AUTHOR  Bo Janko (Tektronix) and Peter Decher (Analogy)
> SOURCE  na
> DATE    na
> PAGES   1-6
>
> TITLE   Return Path Inductance in Measurements of Package Inductance
> Matrixes
> AUTHOR  Brian Young
> SOURCE  IEEE Trans CPMT, Part B, Vol 20, No 1
> DATE    February 1997
> PAGES   50-55
>
> TITLE   TDR Tools in Modeling Interconnects and Packages
> AUTHOR  na
> SOURCE  Tektronix Appication Note
> DATE    1993
> PAGES   1-11
>
> TITLE   The Inductance Matrix of a Multiconductor Transmission Line in
> Multiple
> Magnetic Media
> AUTHOR  Joseph R. Mautz, et. al.
> SOURCE  IEEE Trans on MTT
> VOLUME  36
> NUMBER  8
> DATE    August, 1988
> PAGES   1293-1295
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