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[SI-LIST] Re: Setup-Hold Equations for Source Synchronous Design

  • From: preetesh rathod <preeteshrathod@xxxxxxxxxxx>
  • To: nrpatel@xxxxxxxxxxx, si-list@xxxxxxxxxxxxx
  • Date: Tue, 15 Aug 2006 07:38:55 +0100 (BST)
Hi
   If you want to set up & hold margin calculation particularly for DDR(I) 
SDRAM plz refer
  http://download.intel.com/design/network/desguides/30526103.pdf
   
  This is intel 45X & 46X network processor design guidelines. Refer to DDR 
SDRAM Section. You will be able to find out length constaints theoretically for 
following lines.
  1. Address & Control length with respect to Clock.
  2. DQS length with respect to clock.
  3. Data length with respect to DQS.
   
  For more precise constraints you must do prelayout simulation.
   
  Regards
  Preetesh Rathod
  Design Engineer
  Flextronics Design Ltd., Bangalore.
nrpatel@xxxxxxxxxxx wrote:
  Hello all,
Can someone point me out to a good reference that explains the setup and 
hold margin calculations for a source synchronous design like DDR?
Did not have much luck googling.

Thanks,
Nikhil 



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