FreeLists / si-list / [SI-LIST] DDRAM BUS Testing

["Fraiman, Edi" <Edi.Fraiman@xxxxxxxxxx>]

Hi,
 

I'm working on a design that includes FPGA with DDRAM controller and
several DDRAM chips. The traces goings direct from FPGA to DDRAM with
necessary pulll up resistor to Vref. (SSTL interface) without any debug
connector.

 

Sometimes we have productions problems. It is very difficult to find
what bit in bus between FPGA and DDRAM  is shorted or disconnected.

Could somebody give any tips how it's possible debug DDRAM busses in
terms of production issues. 

 
 
Best regards,
 
Edi Fraiman
 


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