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Thread Index for si-list, 08-2005

[si-list] || [08-2005 Date Index] [08-2005 Thread Index]

  1. [SI-LIST] true differential IBIS problem, TerenceHsieh
  2. [SI-LIST] Thomas M Tokar/Cleveland/RA/Rockwell is out of the office., Thomas M Tokar
  3. [SI-LIST] Question on ground trace in TL, Bi Han
  4. [SI-LIST] Re: ??: Re: How to use Intel's model?, Muranyi, Arpad
  5. [SI-LIST] Asian IBIS Summit First Announcement, Bob Ross
  6. [SI-LIST] Re: true differential IBIS problem, Muranyi, Arpad
  7. [SI-LIST] Re: Question on ground trace in TL, Grasso, Charles
  8. [SI-LIST] Power Integrity Special session at 2005 IEEE EMC symposium in Chicago (8/8-8/12), Zhiping Yang (zhiping)
  9. [SI-LIST] Question on Obtaining Z parameter through VNA, Ivan Zhang
  10. [SI-LIST] Query on Pci Express insertion loss specification, vani.chandrasekharan
  11. [SI-LIST] Ground plane question, Mike S.
  12. [SI-LIST] Re: 回复： Re: Question on Obtaining Z parameter through VNA, Ray Anderson
  13. [SI-LIST] Re: si-list Digest V5 #299, Dmitriev-Zdorov, Vladimir
  14. [SI-LIST] Re: Ground plane question, Curt McNamara
  15. [SI-LIST] Er range of FR4, Grasso, Charles
  16. [SI-LIST] Re: Er range of FR4, Aubrey_Sparkman
  17. [SI-LIST] Package modeling tools, Ambr Amit
  18. [SI-LIST] PCI Express lane to lane skew, vani.chandrasekharan
  19. [SI-LIST] One strange question on my Hspice simulation!, Stephen Wang(Huawei)
  20. [SI-LIST] Re: PCI Express lane to lane skew, Loyer, Jeff
  21. [SI-LIST] hcsl specification, Ray Anderson
  22. [SI-LIST] Crosstalk in time units, vighneshrudra das
  23. [SI-LIST] Re: Crosstalk in time units, Hassan O. Ali
  24. [SI-LIST] C via model -- simple clarification please, John Lipsius
  25. [SI-LIST] Query on Fast slow and typical simulation, vani.chandrasekharan
  26. [SI-LIST] Re: Query on Fast slow and typical simulation, vani.chandrasekharan
  27. [SI-LIST] Off-spec Use of Protection Components, Doug Smith
  28. [SI-LIST] ESD strips on board edge, Thoon, Koh Yew
  29. [SI-LIST] IBIS in hpsice, TerenceHsieh
  30. [SI-LIST] Re: Package modeling tools, Ambr Amit
  31. [SI-LIST] Re: IBIS in hpsice, Aubrey_Sparkman
  32. [SI-LIST] Re: ESD strips on board edge, Pommerenke, David
  33. [SI-LIST] Which layer is better for GHz signals, Ravinder . Ajmani
  34. [SI-LIST] Re: Which layer is better for GHz signals, Mike Greim
  35. [SI-LIST] IDC connector Spice models, alpesh_bhobe
  36. [SI-LIST] Re: Return Path, Abhijit Mahajan
  37. [SI-LIST] 1-2 day contract job -- Crosstalk Survey of a PCB, bbolton
  38. [SI-LIST] Re: si-list Digest V5 #307, Russell Rapport
  39. [SI-LIST] Re: Current Flow, Dimiter Popoff
  40. [SI-LIST] Static power consumption, Dimiter Popoff
  41. [SI-LIST] Re: Static power consumption, Dimiter Popoff
  42. [SI-LIST] 2006 International Symposium on EMC in Singapore, EMC Singapore
  43. [SI-LIST] Current Flow through a capacitor, Eric Bogatin
  44. [SI-LIST] Re: SMPS, Russel Hughes
  45. [SI-LIST] onchip interconnects, their dependence on PVT conditions, pras sirish
  46. [SI-LIST] Re: onchip interconnects, their dependence on PVT conditions, pras sirish
  47. [SI-LIST] SerDes Position, Elias Lozano
  48. [SI-LIST] termination for routing 8 SDRAMs to single Processor, Aravnda G
  49. [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor, Dimiter Popoff
  50. [SI-LIST] Clock Distribution, SanjayKumar Vasamreddy
  51. [SI-LIST] Re: Clock Distribution, steve weir
  52. [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor, Dimiter Popoff
  53. [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor, Dimiter Popoff
  54. [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor, Dimiter Popoff
  55. [SI-LIST] hold time, Yuming Cheng
  56. [SI-LIST] Re: termination for routing 8 SDRAMs to single Pro cessor, Dave Barr
  57. [SI-LIST] model selector, Yuming Cheng
  58. [SI-LIST] Re: termination for routing 8 SDRAMs to single Proc essor, Grasso, Charles
  59. [SI-LIST] DDR2 ODT configuration, Zhuofan Ma
  60. [SI-LIST] Re: Hi and Lo in SigWave, Lance Wang
  61. [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor, steve weir
  62. [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor, Grasso, Charles
  63. [SI-LIST] Simulate 100MHz DRAMs for long term failures?!?!, Loyer, Jeff
  64. [SI-LIST] Re: Simulate 100MHz DRAMs for long term failures?!?!, steve weir
  65. [SI-LIST] Re: Simulate 100MHz DRAMs for long term failures?!?!, steve weir
  66. [SI-LIST] Radiated Emissions, Americomrh
  67. [SI-LIST] driver schedule in hspice, TerenceHsieh
  68. [SI-LIST] Re: DDR2 ODT configuration, hermann.ruckerbauer
  69. [SI-LIST] Regarding PCI protocol analyzers, vani.chandrasekharan
  70. [SI-LIST] Re: Radiated Emissions, Curt McNamara
  71. [SI-LIST] Re: driver schedule in hspice, Muranyi, Arpad
  72. [SI-LIST] Job Opportunity at AMD Colorado, Daugherty, Jay
  73. [SI-LIST] Radiated Emissions continued, Americomrh
  74. [SI-LIST] How to use connector SPICE models Webinar, Julian Ferry
  75. [SI-LIST] Re: Radiated Emissions continued, Curt McNamara
  76. [SI-LIST] Re: termination for routing 8 SDRAMs to single P rocessor, Peterson, James F (FL51)
  77. [SI-LIST] Ringback measuremenr with HSPICE, Khan, Mohammad I
  78. [SI-LIST] unsubscribe, atif shamim
  79. [SI-LIST] GPOF codes ?, Chris Cheng
  80. [SI-LIST] Re: GPOF codes ?, Ray Anderson
  81. [SI-LIST] ADS usage in SI analysis, Bi Han
  82. [SI-LIST] Re: ADS usage in SI analysis, Chris Cheng
  83. [SI-LIST] Should the signals always return back through GND, Nikita nivan
  84. [SI-LIST] Should the signals always return back through GND, nikitanivan
  85. [SI-LIST] Re: Should the signals always return back through GND, art_porter
  86. [SI-LIST] Re: Should the signals always return back through GND, steve weir
  87. [SI-LIST] Effective Curent Source Model, pras sirish
  88. [SI-LIST] Re: Accounting random jitter, Plesa, James T.
  89. [SI-LIST] MiniPCI connector Spice model /IBIS model needed, lsyshen
  90. [SI-LIST] Re: [SI-LIST]: Embedded capacitance on Flex..??, Ray Anderson
  91. [SI-LIST] RF board Vs High speed board, johnn william
  92. [SI-LIST] Skin effect resistance in package pins for IR drop calculations, Mohan R
  93. [SI-LIST] Re: RF board Vs High speed board, Andrew Burnside
  94. [SI-LIST] Re: RF board Vs High speed board ... RF amplifiers, Andrew Burnside
  95. [SI-LIST] subscribe, Nikita nivan
  96. [SI-LIST] SSTL termination resistor power, Bi Han
  97. [SI-LIST] Low Power devices, sunil bharadwaz
  98. [SI-LIST] Measure ESD induced noise, chen, jinhua
  99. [SI-LIST] Errata list for High-Speed Digital System Design by Hall/Hall/McCall?, Curt McNamara
  100. [SI-LIST] Re: Errata list for High-Speed Digital System Design by Hall/Hall/McCall?, steve weir
  101. [SI-LIST] DDR2 ODT options, Bi Han
  102. [SI-LIST] Re: Measure ESD induced noise, chen, jinhua
  103. [SI-LIST] VME connector models, Surjendra Goswami
  104. [SI-LIST] Re: DDR2 ODT options, Peterson, James F (FL51)
  105. [SI-LIST] Fwd: Query, m har
  106. [SI-LIST] Length matching for ZBT, Suresh kumar
  107. [SI-LIST] Question for PSPICE users, Chris Cheng
  108. [SI-LIST] Re: SSTL termination resistor power, Chris Cheng
  109. [SI-LIST] Re: VME connector models, Mike Greim
  110. [SI-LIST] Active capacitance canceling circuitry, Gary Morrell
  111. [SI-LIST] 50 Ohm vs 75 ohm, jen guest
  112. [SI-LIST] Re: 50 Ohm vs 75 ohm, 박철우
  113. [SI-LIST] Power Beaming, Andrew Becker
  114. [SI-LIST] Resistors at High-Frequency, Bill Wurst
  115. [SI-LIST] Driver strength and trace capacitance, Ravinder . Ajmani
  116. [SI-LIST] Re: Driver strength and trace capacitance, steve weir
  117. [SI-LIST] Re: Question for PSPICE users, Chris Cheng
  118. [SI-LIST] A doubt in PADS 2005, nikitanivan
  119. [SI-LIST] test, Doug Smith



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