Go to the FreeLists Home Page Home Signup Help Login
 



[si-list] || [Date Prev] [08-2005 Date Index] [Date Next] || [Thread Prev] [08-2005 Thread Index] [Thread Next]

[SI-LIST] Re: Which layer is better for GHz signals

  • From: Robert Haller <rhaller@xxxxxxxxxx>
  • To: Ravinder.Ajmani@xxxxxxxxxxxxxx
  • Date: Thu, 04 Aug 2005 15:16:14 -0400
Ravinder,
        Great topic, and lots of good discussion. Things to watch
Return path (as pointed out) , Keeping via stubs short, Dielectric losses (~ > 
2Ghz)
Keep Microstrip short if you mix with stripline - PWB processing on outer 
layers is typically additive, on inner layers subtractive - They do not track 
which creates larger impedance mismatchs.

Regards,
Bob Haller
SiSoft



Ravinder.Ajmani@xxxxxxxxxxxxxx wrote:

>Hi All,
>For my next design I am considering a different approach to route the GHz 
>signals.  I would like to know the views of other esteemed SI experts on 
>the following two approaches.
>
>A) Current Design: Differential traces are routed on Top and Bottom 
>layers.  The advantage of this approach is that  I can route one pair 
>without using any vias, and I get more usable board space.  The 
>disadvantage is that traces on Top and Bottom layers have greater 
>impedance discontinuities due to uneven plating and soldermask 
>application. 
>
>B) Proposed Design:  Differential traces will be routed on the inner 
>layers.  The advantage here is that the trace impedance will be more 
>uniform as the trace will be covered with dielectric on both sides, and 
>there will be no plating.  The disadvantage is that  I will have to use 
>two vias on each trace, and I will have less routing space.
>
>The reason for considering the new approach is because of the EMI issues 
>with the previous design traced to common-mode currents.  I am not sure 
>which design will have less common-mode effect, as one design has 
>discontinuities due to plating/soldermask whereas the other design has 
>discontinuities due to extra vias. 
>
>The trace length is about 2 inches.
>
>Regards, Ravinder
>Server PCB Development
>Hitachi Global Storage Technologies
>
>Email: Ravinder.Ajmani@xxxxxxxxxxxxxx
>
>------------------------------------------------------------------
>To unsubscribe from si-list:
>si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
>
>or to administer your membership from a web page, go to:
>http://www.freelists.org/webpage/si-list
>
>For help:
>si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
>
>List FAQ wiki page is located at:
>                http://si-list.org/wiki/wiki.pl?Si-List_FAQ
>
>List technical documents are available at:
>                http://www.si-list.org
>
>List archives are viewable at:     
>               http://www.freelists.org/archives/si-list
>or at our remote archives:
>               http://groups.yahoo.com/group/si-list/messages
>Old (prior to June 6, 2001) list archives are viewable at:
>               http://www.qsl.net/wb6tpu
>  
>
>  
>
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field

List FAQ wiki page is located at:
                http://si-list.org/wiki/wiki.pl?Si-List_FAQ

List technical documents are available at:
                http://www.si-list.org

List archives are viewable at:     
                http://www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu
  





[ Home | Signup | Help | Login | Archives | Lists ]

All trademarks and copyrights within the FreeLists archives are owned by their respective owners.
Everything else ©2007 Avenir Technologies, LLC.