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[SI-LIST] Re: Query on Fast slow and typical simulation

  • From: Istvan Novak <istvan.novak@xxxxxxx>
  • To: vani.chandrasekharan@xxxxxxxxx
  • Date: Thu, 04 Aug 2005 08:49:42 -0400
Vani,

Please note in Jim's excellent summary that when he speaks about
the Fast corner, he says that it is good to check fast-edge-rate effects. 
Meaning that the fast corner is not universally the best corner.
We have to keep in mind that what is best case for the shortest delay,
is actually the worst case for crosstalk saturation, SSN, power-rail
Ldi/dt noise and also for EMI.

Regards,
Istvan Novak
SUN Microsystems


vani.chandrasekharan@xxxxxxxxx wrote:

>=0D
>Thanks for taking the time to explain and clarify. You have further
>kindled my interest in this subject.
>That was great help.
>
>Warm regards
>Vani
>
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>On Behalf Of Jim Antonellis
>Sent: Thursday, August 04, 2005 10:05 AM
>To: Vani Chandrasekharan (WT01 - Software Products & OSS);
>si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: Query on Fast slow and typical simulation
>
>
>Vani,
>
>These represent 3 process corners whereby the devices (CMOS FETs) are
>strong (resulting in fast propagation and edge rates), weak (resulting
>in slow propagation and edge rates), or nominal (which results in
>typical propagation and edge rates).
>
>In simulation, to cover Process-Voltage-Temperature (PVT) variation you
>may run your simulations with the following permutations:
>
>1- Fast (process), High (voltage), Low (temp)
>2- Typ (process), nominal (voltage), nominal (temp)
>3- Slow (process), Low (voltage), high (temp)
>
>Case #1 would be a Best Case (BC) PVT corner, good for testing fast
>edge-rate si effects and hold timing (in a synch system).
>
>Case #3 would be a Worst Case (WC) PVT corner, good for testing slow
>edge-rate si effects and setup timing issues (in a synch sys).
>
>***Please note, these are the traditional effects on CMOS FETS ***and a
>recent posting to this list discussed how deep sub micron ***will
>actually have opposite effects. Also, bipolar designs are ***again
>different. Having said all that, I do believe this is still ***a valid
>explanation, you now need to adapt it to your technology ***and
>requirements.
>
>Regards,
>Jim
>
>
>-
>Jim Antonellis   janton@xxxxxxxxxxxxx
>Sandburst Corp   www.sandburst.com
>Office: 978.689.1669
>Cell: 978.618.4745
>
>This message and any attachments are Confidential and may be Legally
>Privileged. It is intended solely for the addressee. If you are not the
>intended recipient, please delete this message from your system and
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>
>
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx
>[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of
>vani.chandrasekharan@xxxxxxxxx
>Sent: Thursday, August 04, 2005 12:21 AM
>To: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Query on Fast slow and typical simulation
>
>
>
>Hi all,
>
>I was wondering what fast, slow and typical mode of simulation imply. In
>my case all these files are encrypted so could not have much idea about
>these modes.
>
>Considering a Tr-ch-Rx setup, could you help me understand what exactly
>is contained in a spice file describing fast slow and typical modes.
>
>Thanks and warm regards
>Vani
>
>
>  
>

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