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Thread Index for si-list, 08-2004

[si-list] || [08-2004 Date Index] [08-2004 Thread Index]

  1. [SI-LIST] Yet another ASCII Schematic program, Ray Anderson
  2. [SI-LIST] Re: DDR DRAM, Jim Antonellis
  3. [SI-LIST] Re: about XAUI error, Rotem Gazit
  4. [SI-LIST] Max & min parallelism, Budathoki, Trilok (GE Consumer & Industrial)
  5. [SI-LIST] ECL IBIS Models!, G.Srinivasan
  6. [SI-LIST] INFO: IBIS and Simulation Technologies Training is available in San Jose, CA and Austin, TX, Service@wlsi
  7. [SI-LIST] Wi-Fi EMI, Doug Smith
  8. [SI-LIST] Fairchild HSPICE models, sivi.cla@xxxxxxxxx
  9. [SI-LIST] SI Engineer Positions at EMC Corporation, Hopkinton, MA, arsenault, brian
  10. [SI-LIST] Equations for creating twisted pair transmission lines?, tom_cip_11551
  11. [SI-LIST] Measurement peaks of current., Tal Segev
  12. [SI-LIST] Re: Measurement peaks of current., msharpes
  13. [SI-LIST] Re: Sr. Signal Integrity Engineer opportunity, Alan Hilton-Nickel
  14. [SI-LIST] HyperLynx Technical Marketing Engineer, Hargin, Bill
  15. [SI-LIST] Opening for Signal Integrity, Elias Lozano
  16. [SI-LIST] Re: Equations for creating twisted pair transmission lines?, rolf_harjung
  17. [SI-LIST] IBIS model endpoints mismatch errors, Anuj Chakrapani
  18. [SI-LIST] Internal Inductance, Craig Clewell
  19. [SI-LIST] Re: Internal Inductance, Chris Cheng
  20. [SI-LIST] Main attenuation effect of long cables, Chris Chalmers
  21. [SI-LIST] Design guidelines, krish
  22. [SI-LIST] Which noise source is critial?, Zhangkun
  23. [SI-LIST] Transmitter for DDR1 controller DQ, raj singh
  24. [SI-LIST] Re: Main attenuation effect of long cables, Michael Poimboeuf
  25. [SI-LIST] Re: Which noise source is critial?, Zhangkun
  26. [SI-LIST] The driver model of oscillator, Zhangkun
  27. [SI-LIST] EMI Containment, Loganathan, Karthikeyan (GE Consumer & Industrial)
  28. [SI-LIST] Re: EMI Containment, zhangkun 29902
  29. [SI-LIST] Re: Transmitter for DDR1 controller DQ, Jim Antonellis
  30. [SI-LIST] RMCEMC Career Ops page updated, Grasso, Charles
  31. [SI-LIST] To develope SPICE model for IBIS model with Submodel description, Xiaoling Huang
  32. [SI-LIST] RMCEMC Career ops update #2, Charles Grasso
  33. [SI-LIST] RMCEMC presentation now in pdf, Charles Grasso
  34. [SI-LIST] RMCEMC July presentation download available, Grasso, Charles
  35. [SI-LIST] Open Position for Signal Intergity Engineer, Staff, Scott Hemenway
  36. [SI-LIST] IEEE CPMT Society Phoenix Chapter - Aug 17 meeting announcement, Sam Karikalan
  37. [SI-LIST] Bus Analysers/adaptor cards and active probing, Kedar P. Apte
  38. [SI-LIST] Metallic Transmission (UTP modelling), Chris Chalmers
  39. [SI-LIST] Re: Metallic Transmission (UTP modelling), Geoff Stokes
  40. [SI-LIST] Re: HyperLynx Technical Marketing Engineer, Hargin, Bill
  41. [SI-LIST] Regarding rising waveforms in the IBIS models, Jayasree Nayar
  42. [SI-LIST] routing of DDR clock signals, Henrik Gild
  43. [SI-LIST] Re: routing of DDR clock signals, Henrik Gild
  44. [SI-LIST] in the IBIS models, Steve Nguyen
  45. [SI-LIST] Digital IF Receiver, Mohammad Reza Malek Mohammadi
  46. [SI-LIST] power-up sequencing, Nidhir Agrawal
  47. [SI-LIST] Re: IC package, Sol Tatlow
  48. [SI-LIST] HFSS literature, yue xing li
  49. [SI-LIST] Re: Max & min parallelism, Hargin, Bill
  50. [SI-LIST] Re: PCIX Clock routing and connector, Robert_Washburn
  51. [SI-LIST] R matrix of coupled transmission lines, Riaz Sobrany
  52. [SI-LIST] SI Position Open, Seol Byong-Su
  53. [SI-LIST] pci express links, npaul
  54. [SI-LIST] Next UCB High Speed Class in Redwood City, Lee Ritchey
  55. [SI-LIST] Course on Signal Integrity at San Jose State University - Reminder, Ji Zheng
  56. [SI-LIST] Re: SI Simulation of GHz signals, Suresh Subramaniam
  57. [SI-LIST] Error analysis, package_char
  58. [SI-LIST] know a 30 layer PCB manufacturer?, Sol Tatlow
  59. [SI-LIST] Re: Ferrite Bead- Download available., Grasso, Charles
  60. [SI-LIST] Anyone else receiving these messages when posting??, Ray Anderson
  61. [SI-LIST] Connection to cable shields, Chris Chalmers
  62. [SI-LIST] Quantic-EMC, Robert Sefton
  63. [SI-LIST] Power plane / VCC plane as reference for differencial microstrips, Niki Steenkamp
  64. [SI-LIST] Re: Power plane / VCC plane as reference for differencial microstrips, steve weir
  65. [SI-LIST] Re: Adapting the Metallic Transmission (UTP modelling) Part 3 (mistake in part 2), Dr. Howard Johnson
  66. [SI-LIST] FW: Power plane / VCC plane as reference for differential, Senthil Velmurugan
  67. [SI-LIST] HELP, Senthil Velmurugan
  68. [SI-LIST] Re: FW: Power plane / VCC plane as reference for differential, steve weir
  69. [SI-LIST] Re: Connection to cable shields, zhangkun 29902
  70. [SI-LIST] Re: Power plane / VCC plane as reference for differencial microstrips, zhangkun 29902
  71. [SI-LIST] SI work - part or full time endeavor, D
  72. [SI-LIST] Ferrite for USB 2.0 Connector, Nitin Sood
  73. [SI-LIST] OT: Swamped with Out of Office replies..., Niki Steenkamp
  74. [SI-LIST] Re: Power plane / VCC plane as reference for differencial microstrips, steve weir
  75. [SI-LIST] EPEP-2004, Jose Schutt-Aine
  76. [SI-LIST] Hi,all. Does anyone know why DDR address signal with compensation cap is better than without compensation cap? thank you!, Jie J. Zhou
  77. [SI-LIST] Query Regarding DQS line in DDR-SDRAM's, Raghavendra
  78. [SI-LIST] Mounting pad Design??, Kevin Buchanan
  79. [SI-LIST] INFO: Last call for IBIS Training in SanJose, CA and Austin, TX, Service@WLSI
  80. [SI-LIST] Job opening for EDA Application Engineer, HR
  81. [SI-LIST] Internship Available, Daniel Chow
  82. [SI-LIST] Input impedance of Power trace, Charles Grasso
  83. [SI-LIST] Can a thin PCB trace be used as a reliable fuse, Gaitonde, Tilak
  84. [SI-LIST] Re: Can a thin PCB trace be used as a reliable fuse, Nagel, Michael
  85. [SI-LIST] Bypass vs Decoupling capacitors, Ummalaneni, Venu Babu (Venu)
  86. [SI-LIST] Re: low repetation traces crossing splits, kfrobinson
  87. [SI-LIST] Re: Bypass vs Decoupling capacitors, Ray Anderson
  88. [SI-LIST] CPW, Vinod Koul
  89. [SI-LIST] issue in IBIS modelling of LVDS buffer, chandrasekaran.nithya
  90. [SI-LIST] Alternates for PCB solders, Shabdha Brahma
  91. [SI-LIST] Queries regarding SGMII PHY-system level understanding, Gunjan Mandal
  92. [SI-LIST] Re: Bypass vs Decoupling capacitors-thanks, Ummalaneni, Venu Babu (Venu)
  93. [SI-LIST] a puzzling question, suxianxian
  94. [SI-LIST] R: a puzzling question, Guasti Giovanni
  95. [SI-LIST] Re: issue in IBIS modelling of LVDS buffer, Muranyi, Arpad
  96. [SI-LIST] Decoupling for PLL, zhangkun 29902
  97. [SI-LIST] Re: Decoupling for PLL, Nguyen, Mike
  98. [SI-LIST] The frontside groundplane, Jenny Jiang
  99. [SI-LIST] Job Opportunity, Binshen Meng
  100. [SI-LIST] HSPICE vs. Eldo, Chris McGrath
  101. [SI-LIST] Misplaced Query, but guidance sought..., MOHAN GUPTA T V K - RND
  102. [SI-LIST] LVDS center tap capacitor termination, Ummalaneni, Venu Babu (Venu)
  103. [SI-LIST] Re: LVDS center tap capacitor termination, steve weir
  104. [SI-LIST] 90 degree bend, New Bee
  105. [SI-LIST] Re: 90 degree bend, William Kitchen
  106. [SI-LIST] Re: 802.11g/b transmitter duty cycle, John Barnes
  107. [SI-LIST] Unsubscribe, William Yao
  108. [SI-LIST] 90 degree bend -links, Senthil Velmurugan



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