FreeLists / si-list / [SI-LIST] Re: routing of DDR clock signals

[steve weir <weirsp@xxxxxxxxxx>]

Henrik, if you are new at this, you will probably get the best results by=20
treating the pair as a loosely coupled differential pair.  That means=20
providing greater than normal horizontal spacing between the CK and CK#=20
than normal signals.  Then the differential impedance will be close to 2X=20
the normal mode impedance of each line.  Additionally, timing aberrations=20
caused by crosstalk can be reduced by affording 5H spacing between either=20
CK or CK# and the nearest outside neighbor signal.  Remember that you are=20
matching electrical length.  The easiest way to do that is to keep the=20
physical routes reasonably close together and then match physical length.

Steve

At 01:38 PM 8/16/2004 +0200, Henrik Gild wrote:
>Hi!
>
>This is my first post to this list. Looking at some previous posts I'm sure
>you'll be able to answer this one for me:
>
>When routing DDR SDRAM signals (ordinary DDR1, 166MHz, DDR333), should the
>CK and CK# lines be treated as a differential pair or just like any other
>signals (like DQ or DQS) only that they should be of equal length? I had a
>look in the datasheet on the MT46V16M16 from Micron and it didn't say
>anything about differential clock lines, just that the signal edges has to
>coincide time-wise. But the clock signals were described as differential in
>their IBIS model...
>
>Thanks
>/Henrik Gild=E5, B.S.CE
>
>_________________________________________________________________
>Chat: Ha en fest p=E5 Habbo Hotel
>http://habbohotel.msn.se/habbo/sv/channelizer Checka in h=E4r!
>
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