FreeLists / si-list / [SI-LIST] Re: EMI Containment third try is the charm

[steve weir <weirsp@xxxxxxxxxx>]

Vishram, the extra "[1]" breaks the link.  This link works:

http://pcdandm.com/pcdmag/mag/0404/0404pandit.pdf

One of the big themes of that paper is the need to divide the PDS into=20
islands to push up cavity resonant frequencies.  This is readily evidenced=
=20
by the removal of the high peaks at even quarter wave multiples of the=20
original board.  The authors used Sigrity to help refine their design for=20
the desired performance.  But even a nice tool like Sigrity is not going to=
=20
offer a magic way to fix a fundamentally flawed stack-up.

Steve.
At 05:14 AM 8/9/2004 +0000, Vishram Pandit wrote:
>
>Here is the correct link.
>
>http://pcdandm.com/pcdmag/mag/0404/0404pandit.pdf[1]
>
>Thanks,
>
>Vishram
>
>
>
> >From: "Vishram Pandit" <vishrampandit@xxxxxxxxxxx> >Reply-To:
>vishrampandit@xxxxxxxxxxx >To: karthikeyan.loganathan@xxxxxx,
>si-list@xxxxxxxxxxxxx >Subject: [SI-LIST] Re: EMI Containment >Date: Mon,=
 09
>Aug 2004 05:03:35 +0000 >>>Karthik, >>>Here is previously published article
>that delineates the EMI containment >methodology. It also discusses the
>capacitors stitching.
> >>>>http://pcdandm.com/pcdmag/mag/0404/0404pandit.pdf[1] >>>>Thanks,
> >>Vishram Pandit >>>   >From: "Loganathan, Karthikeyan (GE Consumer
>&Industrial)" ><karthikeyan.loganathan@xxxxxx> >Reply-To:
>karthikeyan.loganathan@xxxxxx >>To:<si-list@xxxxxxxxxxxxx> >Subject:
>[SI-LIST] EMI Containment >Date: Sun, >8Aug 2004 19:32:48 +0530 >>Hi All,
> >>Ifound a high speed (operated upto >1Ghz), dense board design total =3D
> >10layers, out of which only one 3.3V >(layer2) Plane and One Gnd Plane =
=3D
> >(layer9). Other Power traces were routed >individually. >>To reduce the
>radiation, they have provided Stitch >Capacitors=3D >(decoupling) between
>layer2 &9, across the board. All the fast >=3D >switching signals were=
 routed
>within these layers. >>I am sure, Stitch >capacitor technique reduces EMI,
>but my question is, =3D >what extent?.  Is >anybetter method available?=
 >>As
>you know, the return current paths in the >stackup said has wide =3D
> >seperation between signal and reference planes, >also the stitch =3D
> >capacitors (SMT) added will have inherent Lead Inductance >and overall =
=3D
> >increases the board cost too. >>Thanks, >Karthik
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>Links --- >    1 http://pcdandm.com/pcdmag/mag/0404/0404pandit.pdf >    2
>http://g.msn.com/8HMBENUS/2752??PS=3D47575
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