FreeLists / si-list / [SI-LIST] Re: EMI Containment

["Vishram Pandit" <vishrampandit@xxxxxxxxxxx>]

Karthik,


Here is previously published article that delineates the EMI containment
methodology. It also discusses the capacitors stitching. 

  

http://pcdandm.com/pcdmag/mag/0404/0404pandit.pdf[1] 

  

Thanks, 

Vishram Pandit 


  >From: "Loganathan, Karthikeyan (GE Consumer &Industrial)"
<karthikeyan.loganathan@xxxxxx> >Reply-To: karthikeyan.loganathan@xxxxxx
>To:<si-list@xxxxxxxxxxxxx> >Subject: [SI-LIST] EMI Containment >Date: Sun,
8Aug 2004 19:32:48 +0530 >>Hi All, >>I found a high speed (operated upto
1Ghz), dense board design total = >10layers, out of which only one 3.3V
(layer2) Plane and One Gnd Plane = >(layer9). Other Power traces were routed
individually. >>To reduce the radiation, they have provided Stitch
Capacitors= >(decoupling) between layer 2 &9, across the board. All the fast
= >switching signals were routed within these layers. >>I am sure, Stitch
capacitor technique reduces EMI, but my question is, = >what extent?.  Is
anybetter method available? >>As you know, the return current paths in the
stackup said has wide = >seperation between signal and reference planes, 
also the stitch = >capacitors (SMT) added will have inherent Lead Inductance
and overall = >increases the board cost too. >>Thanks, >Karthik
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--- Links ---
   1 http://pcdandm.com/pcdmag/mag/0404/0404pandit.pdf
   2 http://g.msn.com/8HMBENUS/2752??PS=47575
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