FreeLists / si-list / [SI-LIST] Re: IBIS model endpoints mismatch errors

["Tom Dagostino" <tom@xxxxxxxxxxxxx>]

Mike

I looked at the model.  All VT curves look normal.  What I did notice was
the end point errors all went away for the rising waveforms with load to
ground when the load resistor went to 67 Ohms.  It looks like there could
have been a setup error.

Tom Dagostino
Teraspeed Consulting Group LLC
503-430-1065
tom@xxxxxxxxxxxxx
www.teraspeed.com

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Mike LaBonte
Sent: Friday, August 06, 2004 9:27 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: IBIS model endpoints mismatch errors


Is the rising waveform actually settling? The number one reason for DC/AC
endpoints mismatch is that the simulation duration was not long enough for
the waveform to flatten out to the final steady-state value.

Mike LaBonte

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Anuj Chakrapani
Sent: Thursday, August 05, 2004 9:45 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] IBIS model endpoints mismatch errors


Hi:
I am generating an IBIS model from the Spice netlists
of I/O buffers available to me. I am using the s2ibis2
method for generation of the IBIS model.
The curves generated look fine. But, the IBISCHK3
parser flags the DC/AC endpoints mismatch error. From
the looks of it, it is obvious that the rising
waveform is settling to a value higher than the DC
endpoint. But, I am trying to figure out why.

Could this be because of the buffer design? Or is this
merely an accuracy issue of the tool used (i.e.,
s2ibis2)?

Your inputs would be much appreciated.

Thanks,
-Anuj.

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