FreeLists / si-list / [SI-LIST] Re: IBIS model endpoints mismatch errors

[Yafei Bi <yafei_bi@xxxxxxxxx>]

Anuj,

s2ibis2 is known to have a lot of issues. so always
examin the every result carefully.

BTW, there is a new & improved s2ibs3 BETA available
at:

http://www.ece.ncsu.edu/erl/ibis/s2ibis3/s2ibis3.htm

As regard to error, there are several possibilities:

1. the .tr simulaiton is terminated earlier before the
output waveform settles down. run it longer.

2. pull up curve are not vcc relative.

3. your supply voltage adn [v_fixture] are not
consistent.


regards,

Yafei
--- Anuj Chakrapani <anuj_asu@xxxxxxxxx> wrote:

> Hi:
> I am generating an IBIS model from the Spice
> netlists
> of I/O buffers available to me. I am using the
> s2ibis2
> method for generation of the IBIS model.
> The curves generated look fine. But, the IBISCHK3
> parser flags the DC/AC endpoints mismatch error.
> From
> the looks of it, it is obvious that the rising
> waveform is settling to a value higher than the DC
> endpoint. But, I am trying to figure out why.
> 
> Could this be because of the buffer design? Or is
> this
> merely an accuracy issue of the tool used (i.e.,
> s2ibis2)?
> 
> Your inputs would be much appreciated.
> 
> Thanks,
> -Anuj.
> 
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> -- Binary/unsupported file stripped by Ecartis --
> -- Type: application/octet-stream
> -- File: opttt_1.ibs
> -- Desc: opttt_1.ibs
> 
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