FreeLists / si-list / [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator

["Abe Riazi" <ariazi@xxxxxxxxxxxxxxx>]

> If you remember the UMR paper on power bus decoupling, it made a clear case
> that the location of the capacitors is relatively unimportant.
 
To be fair, it should be added that different recommendations ( from above) 
exist in literature
regarding optimum location of the decoupling caps.

Two examples follow:

1.  Stephen H.Hall et al., " High-Speed Digital System Design........", on page 
247 it is stated:

" Figure 10.10 suggests not only that the local decoupling capacitor value 
should be chosen
appropriately but that the capacitor is placed physically close to the 
component to minimize
the loop area ".

2. A technical paper by R. Chen, "Where to Place Decoupling Capacitors?..."  
available on
www.sigrity.com web site, implies that the best location for decoupling caps 
needs to
be ascertained with aid of electromagnetic field simulation.

Best Regards,

Abe Riazi
ServerWorks





------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field

List archives are viewable at:     
                http://www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages 
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu