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Thread Index for si-list, 08-2002

[si-list] || [08-2002 Date Index] [08-2002 Thread Index]

  1. [SI-LIST] Re: Layout service recommendations - THINGS TO LOOK FOR, Alex McPheeters
  2. [SI-LIST] Re: Layout service recommendations, Bill Reams
  3. [SI-LIST] Ethernet switch burnout, Jan Vercammen
  4. [SI-LIST] Termination resistors, Ibrahim Khan
  5. [SI-LIST] Re: Output Capacitor of a switching Regulator, Larry Smith
  6. [SI-LIST] Re: Remove Ground underneath Differential signal is deserved or not?, jeff_latourrette
  7. [SI-LIST] Re: Blatant advertising, Alex McPheeters
  8. [SI-LIST] Re: Remove Ground underneath Differential signal isdeserved or not?, Dorin
  9. [SI-LIST] Power supply filtering, Bob Patel
  10. [SI-LIST], cher_rowland
  11. [SI-LIST] Placement of Decoupling Caps, Suresh Sivasubramaniam
  12. [SI-LIST] Autorouting Algorithm?, Inmyung Song
  13. [SI-LIST] Re: Power supply filtering, Ingraham, Andrew
  14. [SI-LIST] Re: Placement of Decoupling Caps, Ingraham, Andrew
  15. [SI-LIST] Re: Remove Ground underneath Differential signal isdeserved or not?, Ye, Xiaoning
  16. [SI-LIST] Series Termination, Adeel Malik
  17. [SI-LIST] Re: Output Capacitor of a switching Regulato, ANAND KURIAKOSE
  18. [SI-LIST] Antwort: Re: Placement of Decoupling Caps, Andreas_Lenkisch
  19. [SI-LIST] Re: Antwort: Re: Placement of Decoupling Caps, Ray Anderson
  20. [SI-LIST] copper-to-copper separation, Ibrahim Khan
  21. [SI-LIST] Re: copper-to-copper separation, JMurphy
  22. [SI-LIST] Re: SSN Measurement, Ingraham, Andrew
  23. [SI-LIST] active probe issues and effects on SI, Douglas C. Smith
  24. [SI-LIST] Re: active probe issues and effects on SI, Michael_Greim
  25. [SI-LIST] Re: Course on Signal Integrity at San Jose State Univ., Suresh Sivasubramaniam
  26. [SI-LIST] Ground plane split widths..., Johnston, Ross
  27. [SI-LIST] Re: A question for the group, MikonCons
  28. [SI-LIST] Re: Ground plane split widths..., Johnston, Ross
  29. [SI-LIST] PCB tracks, Philippe Robert
  30. [SI-LIST] MAX. IDE CABLE Length?, Brahim Koudssi
  31. [SI-LIST] ¦^«H¡G MAX. IDE CABLE Length?, flin
  32. [SI-LIST] Re: PCB tracks, Philippe Robert
  33. [SI-LIST] Eye pattern between QDR and FPGA, Ibrahim Khan
  34. [SI-LIST] Noise on BGA core voltage rail, Anand . Kuriakose
  35. [SI-LIST] Re: MAX. IDE CABLE Length?, Jay Shenoy
  36. [SI-LIST] Re: Eye pattern between QDR and FPGA, Rotem Gazit
  37. [SI-LIST] Re: Noise on BGA core voltage rail, ANAND KURIAKOSE
  38. [SI-LIST] New appnote on PDS design -- XAPP623, Mark Alexander
  39. [SI-LIST] How to modify IBIS model, Hiten Bhagat
  40. [SI-LIST] HSpice or HyperLynx, Alex Horvath
  41. [SI-LIST] LVDS vs RS422, Pauric Hennessy
  42. [SI-LIST] Re: LVDS vs RS422, Ron . J . Morneault
  43. [SI-LIST] ESD Structure in IBIS, Timothy Coyle
  44. [SI-LIST] Re: Remove Ground underneath Differential signal isdeservedor not?, Scott McMorrow
  45. [SI-LIST] Re: HSpice or HyperLynx, Ravinder Ajmani
  46. [SI-LIST] planer capacitors, Bill Mueller
  47. [SI-LIST] Re: ESD Structure in IBIS, ruston, matt
  48. [SI-LIST] Re: si-list Digest V2 #219, Kolstad, Joel (EIP)
  49. [SI-LIST] SSO, Ibrahim Khan
  50. [SI-LIST] ISI, Ibrahim Khan
  51. [SI-LIST] Re: ISI, Khalid Ansari
  52. [SI-LIST] Re: SSO, Khalid Ansari
  53. [SI-LIST] Re: New appnote on PDS design -- XAPP623, Ibrahim Khan
  54. [SI-LIST] Decoupling Capacitors, Kedar P. Apte
  55. [SI-LIST] Re: Decoupling Capacitors, Ismail B - CTD, Chennai.
  56. [SI-LIST] test message #2 -- ignore, Bret Stott
  57. [SI-LIST] DDR-II: SSTL_18 & ODT, Bret Stott
  58. [SI-LIST] DC-DC converter, Sandesh Nanal
  59. [SI-LIST] Query regarding XTK Files, Subramanya C K
  60. [SI-LIST] How to merge noise waveform into passive signal waveform in XTK?, Jack W.C. Lin
  61. [SI-LIST] Bandwidth of Switching Requlators, Anand . Kuriakose
  62. [SI-LIST] Cost Factor of introducing Blind and Buried Vias, Adeel Malik
  63. [SI-LIST] Re: Decoupling Capacitor, Michael_Greim
  64. [SI-LIST] Using Planar Capacitors, Michael Smith
  65. [SI-LIST] Re: One decoupling cap per BGA power pin?, Larry Smith
  66. [SI-LIST] anti-resonance, Ibrahim Khan
  67. [SI-LIST] Re: DDR-II: SSTL_18 & ODT, pgregory
  68. [SI-LIST] Crosstalk Threshold for HSTL and SSTL I/Os, thetariq
  69. [SI-LIST] AW: Re: DDR-II: SSTL_18 & ODT, hermann . ruckerbauer
  70. [SI-LIST] Ibis model for DVI Transmitter, Ched-Chang Chai
  71. [SI-LIST] ** www.hardware-guru.com **, Eitan k
  72. [SI-LIST] Re: Cost Factor of introducing Blind and BuriedVia s, Michael_Greim
  73. [SI-LIST] Lout of VRM, sogo_hsu
  74. [SI-LIST] Re: anti-resonance, Larry Smith
  75. [SI-LIST] Need help with hspice error, Mohammad Ali
  76. [SI-LIST] test - do not read, Jim Sutherland
  77. [SI-LIST] Termination resistor drift, Jim Sutherland
  78. [SI-LIST] PCB West and HDI Expo 2003 Final Call for Abstracts, Ronda Faries
  79. [SI-LIST] Re: lost contact with engineer, Alex McPheeters
  80. [SI-LIST] DDR-II: timing analysis, Bret Stott
  81. [SI-LIST] Off-topic? Questions about measuring power supply ripple/noise (PARD), Dixon, Adam
  82. [SI-LIST] Re: Lout of VRM, Larry Smith
  83. [SI-LIST] East Coast SI / High Speed Design Engineer Available, John Nieznanski
  84. [SI-LIST] IBIS Model providers, Sgammato Chuck-ECS016
  85. [SI-LIST] Matched Length Constaint Approximation for a bus running between 20-50MHz, Adeel Malik
  86. [SI-LIST] How IBIS Simulator works?, Guillaume Turgeon
  87. [SI-LIST] simulation tool frequency setup, ªô¶®¼z
  88. [SI-LIST] TDR and VNA web cast Tues August 20, Eric Bogatin
  89. [SI-LIST] Clock-recovery for Dummies?, Steven Kan
  90. [SI-LIST] Re: simulation tool frequency setup, Ingraham, Andrew
  91. [SI-LIST] Re: Matched Length Constaint Approximation for a bus running between 20-50MHz, Michael Khusid
  92. [SI-LIST] Re: Matched Length Constaint Approximation for abu s ru nning between 20-50MHz, Michael_Greim
  93. [SI-LIST] Re: Matched Length Constaint Approximation for a bus running between 20-50MHz, Ingraham, Andrew
  94. [SI-LIST] Hspice error message?, Brahim Koudssi
  95. [SI-LIST] Scrambled clock, Hora Abu
  96. [SI-LIST] Package probe station vendors..., Nicholas Dugbartey
  97. [SI-LIST] Require Work, SAINT SIMBA
  98. [SI-LIST] What are the best available tools in market for Printed Circuit Board Level Signal Integrity Analysis, Shiraz Bashir
  99. [SI-LIST] Re: Chip caps vs. Tantalum, pwelling
  100. [SI-LIST] Resume' posting to si-list, Ray Anderson
  101. [SI-LIST] Re: Package probe station vendors..., Lewandowski, Bob
  102. [SI-LIST] IPC_2251 draft copy - bulk capacitance query, Lum Wee Mei
  103. [SI-LIST] PCI Routing, Kedar P. Apte
  104. [SI-LIST] HSpice, Alex Horvath
  105. [SI-LIST] Attn. Mir Faiz Mohammad, Zameer Ahmed
  106. [SI-LIST] Test Message for si-list debug, Ray Anderson
  107. [SI-LIST] si-list repaired !, Ray Anderson
  108. [SI-LIST] Damaging LVDS inputs (with embedded termination) using LVPECL voltage swings?, Aguiñaga
  109. [SI-LIST] Re: Damaging LVDS inputs (with embedded termination) using LVPECL voltage swings?, Karen Stoke
  110. [SI-LIST] Re: PCB Design Technique, Javier del Valle
  111. [SI-LIST] Re: Damaging LVDS inputs (with embedded termination) using LVPECLvoltage swings?, Bill . Cohen
  112. [SI-LIST] Re: Dude! You're simulating at Dell...., Michael_Greim
  113. [SI-LIST] source synchronous constraint, zanglinyuan
  114. [SI-LIST] Re: source synchronous constraint, Jack W.C. Lin
  115. [SI-LIST] Fw: Re: source synchronous constraint, zanglinyuan
  116. [SI-LIST] Re: Quantization and Statistical Averaging, john lipsius
  117. [SI-LIST] Dimensional stability after relamination, s . r . madhuchandra
  118. [SI-LIST] Inter Symbol Interference, Alexander Rose
  119. [SI-LIST] Re: FW: Transmission Line Model Tests -resend, Muranyi, Arpad
  120. [SI-LIST] Re: Inter Symbol Interference, Ingraham, Andrew
  121. [SI-LIST] STM1 electrical, Dorin
  122. [SI-LIST] Looking for Chris Brewster, Aubrey_Sparkman
  123. [SI-LIST] SONET Sync card, Ibrahim Khan
  124. [SI-LIST] Re: SONET Sync card, Bill Dempsey
  125. [SI-LIST] FDIP '02/EPEP '02 Reminder, Ray Anderson
  126. [SI-LIST] Measuring Power and Ground Plane Noise, pgregory
  127. [SI-LIST] Re: Measuring Power and Ground Plane Noise, Ray Anderson
  128. [SI-LIST] why eye crosspoint offset, qzheng
  129. [SI-LIST] Re: Eye pattern generation in XTK, Jack W.C. Lin
  130. [SI-LIST] Re: why eye crosspoint offset, Michael_Greim
  131. [SI-LIST] SFF to SFP adapter board, Steeve Gaudreault
  132. [SI-LIST] Re: 22.1 Ohm vs 50 Ohm Termination, Ray Anderson
  133. [SI-LIST] GTL buffers Vref, Gupta, Naveen
  134. [SI-LIST] Re: GTL buffers Vref, Grigoras, Adrian C
  135. [SI-LIST] edge slope in eye diagram, Nosovitski, Alexander
  136. [SI-LIST] General Trace Impedance, Kedar P. Apte
  137. [SI-LIST] September Meeting of RMCEMS Society and local EMC Class, Charles Grasso



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