FreeLists / si-list / [SI-LIST] Eye pattern between QDR and FPGA

["Ibrahim Khan" <ikhan@xxxxxxxxxxxxxxxxxxx>]

SI Gurus,
 
I need to exercise a 32 bit data bus between a QDR and an FPGA.  The
data is HSTL running at 166Mhz clocked on both edges.  Do I need to run
a PRBS stream on every line from FPGA to look at the eye pattern?.
Anybody has a code to generate a PRBS pattern in FPGA.
 
Thanks
Ibrahim Khan

------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field

List archives are viewable at:     
                http://www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages 
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu