FreeLists / si-list / 08-2002

Date Index for si-list, 08-2002

[si-list] || [08-2002 Date Index] [08-2002 Thread Index]

[SI-LIST] Re: Layout service recommendations - THINGS TO LOOK FOR - Alex McPheeters
[SI-LIST] Re: Layout service recommendations - Bill Reams
[SI-LIST] Ethernet switch burnout - Jan Vercammen
[SI-LIST] Termination resistors - Ibrahim Khan
[SI-LIST] Re: Output Capacitor of a switching Regulator - Larry Smith
[SI-LIST] Re: Remove Ground underneath Differential signal is deserved or not? - jeff_latourrette
[SI-LIST] Re: Layout service recommendations - Alex McPheeters
[SI-LIST] Re: Layout service recommendations - Greg Beck
[SI-LIST] Re: Blatant advertising - Alex McPheeters
[SI-LIST] Re: Layout service recommendations - Doug Brooks
[SI-LIST] Re: Ethernet switch burnout - Ghazzali Majeed
[SI-LIST] Re: Layout service recommendations - Alex McPheeters
[SI-LIST] Re: Layout service recommendations - Martin Euredjian
[SI-LIST] Re: Layout service recommendations - Moran, Brian P
[SI-LIST] Re: Layout service recommendations - Rich Peyton
[SI-LIST] Re: Remove Ground underneath Differential signal isdeserved or not? - Dorin
[SI-LIST] Power supply filtering - Bob Patel
[SI-LIST] Re: Power supply filtering - Doug McKean
[SI-LIST] - cher_rowland
[SI-LIST] Re: Power supply filtering - Val Mandrusov
[SI-LIST] Placement of Decoupling Caps - Suresh Sivasubramaniam
[SI-LIST] Re: Placement of Decoupling Caps - Ray Anderson
[SI-LIST] Autorouting Algorithm? - Inmyung Song
[SI-LIST] Re: Power supply filtering - Ingraham, Andrew
[SI-LIST] Re: Placement of Decoupling Caps - Ingraham, Andrew
[SI-LIST] Re: Remove Ground underneath Differential signal isdeserved or not? - Ye, Xiaoning
[SI-LIST] Series Termination - Adeel Malik
[SI-LIST] Re: Output Capacitor of a switching Regulato - ANAND KURIAKOSE
[SI-LIST] Re: Placement of Decoupling Caps - Ray Anderson
[SI-LIST] Re: Series Termination - Inmyung Song
[SI-LIST] Antwort: Re: Placement of Decoupling Caps - Andreas_Lenkisch
[SI-LIST] Re: Remove Ground underneath Differential signal isdeserved or not? - Dorin
[SI-LIST] Re: Antwort: Re: Placement of Decoupling Caps - Ray Anderson
[SI-LIST] Re: Output Capacitor of a switching Regulato - Larry Smith
[SI-LIST] Re: Placement of Decoupling Caps - Ray Anderson
[SI-LIST] copper-to-copper separation - Ibrahim Khan
[SI-LIST] Re: copper-to-copper separation - JMurphy
[SI-LIST] Re: copper-to-copper separation - Jackson, T L
[SI-LIST] Re: copper-to-copper separation - Jeff Seeger
[SI-LIST] Re: Layout service recommendations - Jeff Seeger
[SI-LIST] Re: copper-to-copper separation - Ingraham, Andrew
[SI-LIST] Re: SSN Measurement - Ingraham, Andrew
[SI-LIST] Re: Power supply filtering - Bob Patel
[SI-LIST] Re: copper-to-copper separation - jeff_latourrette
[SI-LIST] Re: copper-to-copper separation - Lfresearch
[SI-LIST] Re: copper-to-copper separation - John Barnes
[SI-LIST] active probe issues and effects on SI - Douglas C. Smith
[SI-LIST] Re: active probe issues and effects on SI - Michael_Greim
[SI-LIST] Re: Course on Signal Integrity at San Jose State Univ. - Suresh Sivasubramaniam
[SI-LIST] Re: Antwort: Re: Placement of Decoupling Caps - Istvan Novak
[SI-LIST] Re: Antwort: Re: Placement of Decoupling Caps - John Barnes
[SI-LIST] Ground plane split widths... - Johnston, Ross
[SI-LIST] Re: Antwort: Re: Placement of Decoupling Caps - John Barnes
[SI-LIST] Re: A question for the group - MikonCons
[SI-LIST] Re: Antwort: Re: Placement of Decoupling Caps - Raj Raghuram
[SI-LIST] Re: Ground plane split widths... - Johnston, Ross
[SI-LIST] Re: Remove Ground underneath Differential signal is deserved or not? - yunnan
[SI-LIST] PCB tracks - Philippe Robert
[SI-LIST] Re: Antwort: Re: Placement of Decoupling Caps - Istvan Novak
[SI-LIST] Re: PCB tracks - john lipsius
[SI-LIST] Re: PCB tracks - John Barnes
[SI-LIST] Re: Antwort: Re: Placement of Decoupling Caps - ruston, matt
[SI-LIST] Re: Remove Ground underneath Differential signal isdeserved or not? - Scott McMorrow
[SI-LIST] Re: Antwort: Re: Placement of Decoupling Caps - John Barnes
[SI-LIST] Re: Antwort: Re: Placement of Decoupling Caps - Ibrahim Khan
[SI-LIST] Re: Ground plane split widths... - Alan Hilton-Nickel
[SI-LIST] MAX. IDE CABLE Length? - Brahim Koudssi
[SI-LIST] ¦^«H¡G MAX. IDE CABLE Length? - flin
[SI-LIST] ¦^«H¡G MAX. IDE CABLE Length? - flin
[SI-LIST] ¦^«H¡G MAX. IDE CABLE Length? - flin
[SI-LIST] Re: MAX. IDE CABLE Length? - Drew
[SI-LIST] Problems with a post: Re: ¦^«H¡G MAX. IDE CABLE Length? - Drew
[SI-LIST] Re: Ground plane split widths... - Johnston, Ross
[SI-LIST] Re: Ground plane split widths... - Johnston, Ross
[SI-LIST] Re: Remove Ground underneath Differential signal isdeserved or not? - yun
[SI-LIST] Re: PCB tracks - Philippe Robert
[SI-LIST] Re: PCB tracks - gurunath vinayakrao kulkarni
[SI-LIST] Re: MAX. IDE CABLE Length? - John Barnes
[SI-LIST] Re: Ground plane split widths... - Alan Hilton-Nickel
[SI-LIST] Eye pattern between QDR and FPGA - Ibrahim Khan
[SI-LIST] Re: PCB tracks - cadpro2k
[SI-LIST] Noise on BGA core voltage rail - Anand . Kuriakose
[SI-LIST] Re: MAX. IDE CABLE Length? - Jay Shenoy
[SI-LIST] Re: Eye pattern between QDR and FPGA - Rotem Gazit
[SI-LIST] Re: Noise on BGA core voltage rail - ANAND KURIAKOSE
[SI-LIST] Re: PCB tracks - LATOURRETTE,JEFF (A-SanJose,ex1)
[SI-LIST] Re: PCB tracks - Ritchey Lee
[SI-LIST] Re: Noise on BGA core voltage rail - Larry Smith
[SI-LIST] Re: Noise on BGA core voltage rail - Ibrahim Khan
[SI-LIST] Re: Noise on BGA core voltage rail - ANAND KURIAKOSE
[SI-LIST] Re: Noise on BGA core voltage rail - Larry Smith
[SI-LIST] Re: Noise on BGA core voltage rail - Larry Smith
[SI-LIST] Re: Noise on BGA core voltage rail - pwelling
[SI-LIST] Re: PCB tracks - Alan Hilton-Nickel
[SI-LIST] New appnote on PDS design -- XAPP623 - Mark Alexander
[SI-LIST] Re: PCB tracks - Doug Brooks
[SI-LIST] Re: PCB tracks - ray_waugh
[SI-LIST] How to modify IBIS model - Hiten Bhagat
[SI-LIST] HSpice or HyperLynx - Alex Horvath
[SI-LIST] Re: Noise on BGA core voltage rail - ANAND KURIAKOSE
[SI-LIST] LVDS vs RS422 - Pauric Hennessy
[SI-LIST] Re: PCB tracks - gurunath vinayakrao kulkarni
[SI-LIST] Re: Eye pattern between QDR and FPGA - gurunath vinayakrao kulkarni
[SI-LIST] Re: PCB tracks - Ismail B - CTD, Chennai.
[SI-LIST] Re: LVDS vs RS422 - Ron . J . Morneault
[SI-LIST] Re: PCB tracks - ray_waugh
[SI-LIST] Re: HSpice or HyperLynx - Todd Westerhoff
[SI-LIST] ESD Structure in IBIS - Timothy Coyle
[SI-LIST] Re: Remove Ground underneath Differential signal isdeservedor not? - Scott McMorrow
[SI-LIST] Re: Noise on BGA core voltage rail - Larry Smith
[SI-LIST] Re: HSpice or HyperLynx - Ravinder Ajmani
[SI-LIST] Re: Noise on BGA core voltage rail - Bob Patel
[SI-LIST] Re: ESD Structure in IBIS - Abhijit Mahajan
[SI-LIST] planer capacitors - Bill Mueller
[SI-LIST] Re: HSpice or HyperLynx - Bill Hargin
[SI-LIST] Re: ESD Structure in IBIS - ruston, matt
[SI-LIST] Re: si-list Digest V2 #219 - Kolstad, Joel (EIP)
[SI-LIST] Re: Noise on BGA core voltage rail - ANAND KURIAKOSE
[SI-LIST] Re: Noise on BGA core voltage rail - ANAND KURIAKOSE
[SI-LIST] Re: ESD Structure in IBIS - Umesh Painaik
[SI-LIST] Re: HSpice or HyperLynx - Silvano Bettinzana
[SI-LIST] Re: PCB tracks - Istvan Novak
[SI-LIST] Re: PCB tracks - John Howard
[SI-LIST] SSO - Ibrahim Khan
[SI-LIST] ISI - Ibrahim Khan
[SI-LIST] Re: ISI - Douglas Burns
[SI-LIST] Re: ISI - Khalid Ansari
[SI-LIST] Re: SSO - Khalid Ansari
[SI-LIST] Re: HSpice or HyperLynx - Ravinder Ajmani
[SI-LIST] Re: New appnote on PDS design -- XAPP623 - Ibrahim Khan
[SI-LIST] Re: ISI - Ibrahim Khan
[SI-LIST] Re: PCB tracks - ray_waugh
[SI-LIST] Re: HSpice or HyperLynx - Alex Horvath
[SI-LIST] Decoupling Capacitors - Kedar P. Apte
[SI-LIST] Re: PCB tracks - istvan novak
[SI-LIST] Re: Decoupling Capacitors - Ismail B - CTD, Chennai.
[SI-LIST] Re: PCB tracks - Richard A. Schumacher
[SI-LIST] Re: ISI - jeff_latourrette
[SI-LIST] test message #2 -- ignore - Bret Stott
[SI-LIST] test message #2 -- ignore - Bret Stott
[SI-LIST] Re: SSO - Muranyi, Arpad
[SI-LIST] Re: New appnote on PDS design -- XAPP623 - pwelling
[SI-LIST] Noise on Vcore - Sandesh Nanal
[SI-LIST] Re: SSO - Khalid Ansari
[SI-LIST] DDR-II: SSTL_18 & ODT - Bret Stott
[SI-LIST] Re: ISI - evillaf
[SI-LIST] Re: SSO - Muranyi, Arpad
[SI-LIST] DC-DC converter - Sandesh Nanal
[SI-LIST] Re: Noise on BGA core voltage rail - istvan novak
[SI-LIST] Query regarding XTK Files - Subramanya C K
[SI-LIST] Re: Query regarding XTK Files - Tadashi Arai
[SI-LIST] Re: planer capacitors - Tadashi Arai
[SI-LIST] Re: HSpice or HyperLynx - Tadashi Arai
[SI-LIST] How to merge noise waveform into passive signal waveform in XTK? - Jack W.C. Lin
[SI-LIST] Bandwidth of Switching Requlators - Anand . Kuriakose
[SI-LIST] Decoupling Capacitor - Nagaraj
[SI-LIST] Cost Factor of introducing Blind and Buried Vias - Adeel Malik
[SI-LIST] Re: Decoupling Capacitor - John Barnes
[SI-LIST] Re: Decoupling Capacitor - Michael_Greim
[SI-LIST] Eye pattern generation in XTK - Siva kumar
[SI-LIST] Eye pattern generation in XTK - Siva kumar
[SI-LIST] Using Planar Capacitors - Michael Smith
[SI-LIST] Re: One decoupling cap per BGA power pin? - Larry Smith
[SI-LIST] Re: One decoupling cap per BGA power pin? - Ibrahim Khan
[SI-LIST] anti-resonance - Ibrahim Khan
[SI-LIST] Re: One decoupling cap per BGA power pin? - Larry Smith
[SI-LIST] Re: DDR-II: SSTL_18 & ODT - pgregory
[SI-LIST] Re: Cost Factor of introducing Blind and Buried Vias - istvan novak
[SI-LIST] Re: Eye pattern generation in XTK - Tadashi Arai
[SI-LIST] Crosstalk Threshold for HSTL and SSTL I/Os - thetariq
[SI-LIST] AW: Re: DDR-II: SSTL_18 & ODT - hermann . ruckerbauer
[SI-LIST] Ibis model for DVI Transmitter - Ched-Chang Chai
[SI-LIST] ** www.hardware-guru.com ** - Eitan k
[SI-LIST] Re: Using Planar Capacitors - Ege Engin
[SI-LIST] Re: Bandwidth of Switching Requlators - istvan novak
[SI-LIST] Re: Cost Factor of introducing Blind and BuriedVia s - Michael_Greim
[SI-LIST] Lout of VRM - sogo_hsu
[SI-LIST] Re: HSpice or HyperLynx - Alex Horvath
[SI-LIST] Re: anti-resonance - Larry Smith
[SI-LIST] Need help with hspice error - Mohammad Ali
[SI-LIST] Re: Need help with hspice error - Kim Helliwell
[SI-LIST] Re: Need help with hspice error - Brahim Koudssi
[SI-LIST] Re: Need help with hspice error - Kim Helliwell
[SI-LIST] test - do not read - Jim Sutherland
[SI-LIST] Termination resistor drift - Jim Sutherland
[SI-LIST] PCB West and HDI Expo 2003 Final Call for Abstracts - Ronda Faries
[SI-LIST] Re: lost contact with engineer - Alex McPheeters
[SI-LIST] Re: AW: Re: DDR-II: SSTL_18 & ODT - Bret Stott
[SI-LIST] DDR-II: timing analysis - Bret Stott
[SI-LIST] Re: New appnote on PDS design -- XAPP623 - Mark Alexander
[SI-LIST] Re: Lout of VRM - istvan novak
[SI-LIST] Re: DDR-II: timing analysis - john lipsius
[SI-LIST] Off-topic? Questions about measuring power supply ripple/noise (PARD) - Dixon, Adam
[SI-LIST] Re: Off-topic? Questions about measuring power supply ripple/noise (PARD) - istvan novak
[SI-LIST] Re: Lout of VRM - sogo_hsu
[SI-LIST] Re: DDR-II: timing analysis - Bret Stott
[SI-LIST] Re: Lout of VRM - Larry Smith
[SI-LIST] East Coast SI / High Speed Design Engineer Available - John Nieznanski
[SI-LIST] IBIS Model providers - Sgammato Chuck-ECS016
[SI-LIST] Matched Length Constaint Approximation for a bus running between 20-50MHz - Adeel Malik
[SI-LIST] How IBIS Simulator works? - Guillaume Turgeon
[SI-LIST] simulation tool frequency setup - ��z
[SI-LIST] TDR and VNA web cast Tues August 20 - Eric Bogatin
[SI-LIST] Clock-recovery for Dummies? - Steven Kan
[SI-LIST] Re: simulation tool frequency setup - Ingraham, Andrew
[SI-LIST] Re: Matched Length Constaint Approximation for a bus running between 20-50MHz - Michael Khusid
[SI-LIST] Re: Matched Length Constaint Approximation for abu s ru nning between 20-50MHz - Michael_Greim
[SI-LIST] Re: Matched Length Constaint Approximation for a bus running between 20-50MHz - Michael Smith
[SI-LIST] Re: Matched Length Constaint Approximation for a bus running between 20-50MHz - Ingraham, Andrew
[SI-LIST] Re: Matched Length Constaint Approximation for a bus running between 20-50MHz - Michael Khusid
[SI-LIST] Re: Query regarding XTK Files - Abe Riazi
[SI-LIST] Re: Clock-recovery for Dummies? - Jon Keeble
[SI-LIST] Re: DDR-II: timing analysis - john lipsius
[SI-LIST] Re: One decoupling cap per BGA power pin? - john lipsius
[SI-LIST] Hspice error message? - Brahim Koudssi
[SI-LIST] Scrambled clock - Hora Abu
[SI-LIST] Re: Matched Length Constaint Approximation for a bus running between 20-50MHz - Adeel Malik
[SI-LIST] Re: One decoupling cap per BGA power pin? - john lipsius
[SI-LIST] Re: Hspice error message? - Mohammad Ali
[SI-LIST] Re: Hspice error message? - Mike LaBonte
[SI-LIST] Re: Clock-recovery for Dummies? - John Coupland
[SI-LIST] Chip caps vs. Tantalum - Martin Euredjian
[SI-LIST] Re: Clock-recovery for Dummies? - John Coupland
[SI-LIST] Re: Clock-recovery for Dummies? - Alex McPheeters
[SI-LIST] Package probe station vendors... - Nicholas Dugbartey
[SI-LIST] Require Work - SAINT SIMBA
[SI-LIST] What are the best available tools in market for Printed Circuit Board Level Signal Integrity Analysis - Shiraz Bashir
[SI-LIST] Re: Chip caps vs. Tantalum - pwelling
[SI-LIST] Resume' posting to si-list - Ray Anderson
[SI-LIST] Re: DDR-II: SSTL_18 & ODT - Bret Stott
[SI-LIST] Re: Chip caps vs. Tantalum - Ravinder Ajmani
[SI-LIST] Re: Package probe station vendors... - Lewandowski, Bob
[SI-LIST] Re: Package probe station vendors... - istvan novak
[SI-LIST] IPC_2251 draft copy - bulk capacitance query - Lum Wee Mei
[SI-LIST] Re: Chip caps vs. Tantalum - Lewandowski, Bob
[SI-LIST] AW: Re: DDR-II: SSTL_18 & ODT - hermann . ruckerbauer
[SI-LIST] PCI Routing - Kedar P. Apte
[SI-LIST] Re: Chip caps vs. Tantalum - Fasig, Jonathan L.
[SI-LIST] Re: Chip caps vs. Tantalum - Ingraham, Andrew
[SI-LIST] HSpice - Alex Horvath
[SI-LIST] Attn. Mir Faiz Mohammad - Zameer Ahmed
[SI-LIST] Test Message for si-list debug - Ray Anderson
[SI-LIST] si-list repaired ! - Ray Anderson
[SI-LIST] Damaging LVDS inputs (with embedded termination) using LVPECL voltage swings? - Agui�aga
[SI-LIST] Re: Damaging LVDS inputs (with embedded termination) using LVPECL voltage swings? - Karen Stoke
[SI-LIST] Re: PCB Design Technique - Javier del Valle
[SI-LIST] Re: HSpice - Tracy Barclay
[SI-LIST] Re: Damaging LVDS inputs (with embedded termination) using LVPECLvoltage swings? - Bill . Cohen
[SI-LIST] Re: Dude! You're simulating at Dell.... - Michael_Greim
[SI-LIST] Re: Damaging LVDS inputs (with embedded termination) using LVPECL voltage swings? - Allan Davidson
[SI-LIST] source synchronous constraint - zanglinyuan
[SI-LIST] Re: source synchronous constraint - Jack W.C. Lin
[SI-LIST] Re: source synchronous constraint - zanglinyuan
[SI-LIST] Re: source synchronous constraint - Scott McMorrow
[SI-LIST] Re: source synchronous constraint - Scott McMorrow
[SI-LIST] Re: source synchronous constraint - Keven Hui
[SI-LIST] Fw: Re: source synchronous constraint - zanglinyuan
[SI-LIST] Re: Quantization and Statistical Averaging - john lipsius
[SI-LIST] Dimensional stability after relamination - s . r . madhuchandra
[SI-LIST] Re: Quantization and Statistical Averaging - Ingraham, Andrew
[SI-LIST] Re: Quantization and Statistical Averaging - Ingraham, Andrew
[SI-LIST] Inter Symbol Interference - Alexander Rose
[SI-LIST] Re: Fw: Re: source synchronous constraint - Vinu Arumugham
[SI-LIST] Re: source synchronous constraint - Ingraham, Andrew
[SI-LIST] Re: FW: Transmission Line Model Tests -resend - Muranyi, Arpad
[SI-LIST] Re: Inter Symbol Interference - Bill Chen
[SI-LIST] Re: source synchronous constraint - Todd Westerhoff
[SI-LIST] Re: Dimensional stability after relamination - Jeff Seeger
[SI-LIST] Re: Inter Symbol Interference - john lipsius
[SI-LIST] Re: Fw: Re: source synchronous constraint - Mike Brown
[SI-LIST] Re: Inter Symbol Interference - Ingraham, Andrew
[SI-LIST] STM1 electrical - Dorin
[SI-LIST] Looking for Chris Brewster - Aubrey_Sparkman
[SI-LIST] SONET Sync card - Ibrahim Khan
[SI-LIST] Re: SONET Sync card - Bill Dempsey
[SI-LIST] FDIP '02/EPEP '02 Reminder - Ray Anderson
[SI-LIST] Measuring Power and Ground Plane Noise - pgregory
[SI-LIST] Re: Measuring Power and Ground Plane Noise - Ray Anderson
[SI-LIST] Re: Measuring Power and Ground Plane Noise - Virendra
[SI-LIST] Re: Measuring Power and Ground Plane Noise - Ray Anderson
[SI-LIST] Re: Measuring Power and Ground Plane Noise - Chris Padilla
[SI-LIST] why eye crosspoint offset - qzheng
[SI-LIST] Re: Eye pattern generation in XTK - Jack W.C. Lin
[SI-LIST] Re: Ground plane split widths... - Jack W.C. Lin
[SI-LIST] Re: why eye crosspoint offset - Michael_Greim
[SI-LIST] SFF to SFP adapter board - Steeve Gaudreault
[SI-LIST] Re: Measuring Power and Ground Plane Noise - Khalid Ansari
[SI-LIST] Re: 22.1 Ohm vs 50 Ohm Termination - Ray Anderson
[SI-LIST] Re: 22.1 Ohm vs 50 Ohm Termination - Robert_Washburn
[SI-LIST] Re: 22.1 Ohm vs 50 Ohm Termination - Ingraham, Andrew
[SI-LIST] Re: 22.1 Ohm vs 50 Ohm Termination - Dunbar, Tony
[SI-LIST] GTL buffers Vref - Gupta, Naveen
[SI-LIST] Re: GTL buffers Vref - Grigoras, Adrian C
[SI-LIST] Re: 22.1 Ohm vs 50 Ohm Termination - Ibrahim Khan
[SI-LIST] Re: GTL buffers Vref - Grigoras, Adrian C
[SI-LIST] Re: GTL buffers Vref - ruston, matt
[SI-LIST] Re: 22.1 Ohm vs 50 Ohm Termination - Ingraham, Andrew
[SI-LIST] Re: GTL buffers Vref - Samuel Dadel
[SI-LIST] edge slope in eye diagram - Nosovitski, Alexander
[SI-LIST] General Trace Impedance - Kedar P. Apte
[SI-LIST] September Meeting of RMCEMS Society and local EMC Class - Charles Grasso