FreeLists / si-list / [SI-LIST] R: R: Too much predicted loss

["Guasti Giovanni" <Giovanni.Guasti@xxxxxxxxxx>]

Yang,
if your simulated pcb is a little thinner than the actual board it could =
be that line impedance in your measure is higher than line impedance in =
the simulation. Could it be just a problem of impedance mismatch (and =
not of loss)?=20
Could you check the simulated and measured S11 too? (or make a TDR =
measure and see if the impedance is the same of your simulation)
Regards,
        Giovanni

When I have problems with Ansoft I use to call Giancarlo Guida =
(gguida@xxxxxxxxxx) He always find out the solution




-----Messaggio originale-----
Da: You, Yang [mailto:yang.you@xxxxxx]
Inviato: mercoled=EC 13 luglio 2005 15.40
A: Istvan novak; Guasti Giovanni
Cc: si-list@xxxxxxxxxxxxx; Ing. Giancarlo Guida
Oggetto: RE: [SI-LIST] R: Too much predicted loss


Istvan, Guasti,
        Thanks for your reply. This is for a 6 inch, 10 mil trace on the
top layer of a board. The difference between the simulation and
laboratory data is clear from 0 MHz but it deviates more and more after
2 GHz. Using connector models only worsens the results. I've tried
doubling the thickness of the copper as well as adjusting the dielectric
constant and loss tangent values without improvement. Any other ideas?

Yang You

-----Original Message-----
From: Istvan novak [mailto:istvan.novak@xxxxxxx]=20
Sent: Wednesday, July 13, 2005 7:52 AM
To: Giovanni.Guasti@xxxxxxxxxx
Cc: You, Yang; si-list@xxxxxxxxxxxxx; Ing. Giancarlo Guida
Subject: Re: [SI-LIST] R: Too much predicted loss

Well, 8dB sounds like a lot, but the first questions in my mind:
- at what frequency?
- for what length?
- with what kind of connections at the ends?

Regards,

Istvan Novak
SUN MIcrosystems


Guasti Giovanni wrote:

>I don't think a little change in dielectric thickness could change =3D
>losses of 8dB.
>What about the real thickness of copper? depending on pcb manufacturer,
=3D
>layers where via and buried holes start and end increase their
thickness =3D
>(for example top and bottom) for exampre from 18um to 30-40um. So
losses =3D
>can reduce if your traces are on that kind of layers.
>Hope this help
>       Giovanni
>
>
>
>-----Messaggio originale-----
>Da: You, Yang [mailto:yang.you@xxxxxx]
>Inviato: marted=3DEC 12 luglio 2005 18.10
>A: si-list@xxxxxxxxxxxxx
>Oggetto: [SI-LIST] Too much predicted loss
>
>
>Hi,
>            I'm working with the SIWave software on a board with some
>test traces but the results of the simulation indicate about 8 db more
>loss than is actually seen in the lab on the actual board. I imported
>the board directly from the layout tool and setup the stackup but I
>think the dielectric layers I specified might be a little thinner than
>on the actual board. Would that cause more loss to show up in the
>s-parameters? What other factors might be contributing to this? Thanks
>for your help.
>
>=3D20
>
>Yang You
>
>=3D20
>
>Texas Instruments, Inc.
>
> =20
>
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