FreeLists / si-list / [SI-LIST] Balancing Copper and dielectric losses?

["Loyer, Jeff" <jeff.loyer@xxxxxxxxx>]

Leonard,
In this posting, it's implied that there's some benefit to balancing the
dielectric and copper losses.  Is this merely a boo-boo, or is there
some phenomena I haven't heard of?

I'm also surprised to hear the "wonders for group delay" comment.  Can
you clarify what you mean by that?

Jeff Loyer


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Leonard Dieguez
Sent: Wednesday, July 06, 2005 11:34 AM
To: steve weir; leonard.dieguez; rsefton@xxxxxxxxxxxxx;
Charles.Grasso@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Q on Trace Width and Jitter for Diff Pairs

Steve,

I agree with you that you need the "right amount". For a given material
and bit rate there is always the right trace width if you want to
balance the dielectric loss to the copper loss.=3D20

So for short interconnect I feel the problem would be creating a
resonator or sharp filter. Impedance matching really becomes harder
problem. I will normally use a 3D EM simulator like Ansoft HFSS to
simulate each structure then do a end to end simulation. In this case I
would try to excite the two points that we are worried about resonating.
One problem with FR4 is that it is not well behaved and it does wonders
for group delay. It is also hard to simulate if you want to take that
into account. By the time you get PCBs back the "Mixture" may not be
exactly what you thought it was.

Leonard. =3D20

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