FreeLists / si-list / [SI-LIST] Re: Q on Trace Width and Jitter for Diff Pairs

["Leonard Dieguez" <leonard.dieguez@xxxxxxxxxx>]

Steve,

I agree with you that you need the "right amount". For a given material
and bit rate there is always the right trace width if you want to
balance the dielectric loss to the copper loss.=20

So for short interconnect I feel the problem would be creating a
resonator or sharp filter. Impedance matching really becomes harder
problem. I will normally use a 3D EM simulator like Ansoft HFSS to
simulate each structure then do a end to end simulation. In this case I
would try to excite the two points that we are worried about resonating.
One problem with FR4 is that it is not well behaved and it does wonders
for group delay. It is also hard to simulate if you want to take that
into account. By the time you get PCBs back the "Mixture" may not be
exactly what you thought it was.

Leonard. =20

-----Original Message-----
From: steve weir [mailto:weirsi@xxxxxxxxxx]=20
Sent: Wednesday, July 06, 2005 9:50 AM
To: leonard.dieguez; rsefton@xxxxxxxxxxxxx; Charles.Grasso@xxxxxxxxxxxx;
si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: Q on Trace Width and Jitter for Diff Pairs

Leonard, What we want is Goldilocks loss, just enough.  In a backplane,
we=20
always seem to get more than we want.  However for short interconnects=20
beware really low-loss materials.  In those cases, FR4 can be an easier
to=20
manage choice in addition to being cheaper.

Steve.
At 07:19 AM 7/6/2005 -0700, Leonard Dieguez wrote:
>Robert,
>
>DJ, has a few different components. There is jitter that is correlated
>to the data and jitter that is not correlated. An example of
>uncorrelated jitter would be switching power supply noise that would
>make it way into the transmitter or the data stream somehow. Correlated
>jitter also comes in a few forms as well. Jitter cause by impedance
>discontinuities fall into Data dependant jitter. In most normal
>applications of High speed signaling this type of jitter is hard to
>counteract. I will normally stress this to customers and put a lot of
>attention into designing vias, BGA breakouts, connector breakouts,
>surface mount component selection and layout and other PCB
structures.=3D20
>
>Another form of DJ that we all commonly see at multi gigabit speeds is
>Inter-symbol Interference. This is caused by the frequency dependencies
>of the transmission channel. FR4 is one of the worst offenders. In
>simplistic terms you can think of your FR4 PCB as a low pass filter.
The
>higher frequency components are attenuated and the lower frequencies
are
>passed. One thing that happens is that the bit energy will get smeared
>over time so you have the situation where a nice crisp rising or
falling
>edge is input to the channel and at the output of the channel the
>falling edge will cover several bit times. Since our goal is to have
our
>edge to occur within one bit time we have techniques to counter some of
>the effects of ISI, mainly transmit equalization (pre emphasis) and
>receive equalization (continuous time and DFE).=3D20
>
>Leonard Dieguez
>System IO Specialist.
>
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
>On Behalf Of Robert Sefton
>Sent: Tuesday, July 05, 2005 3:23 PM
>To: Charles.Grasso@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: Q on Trace Width and Jitter for Diff Pairs
>
>Hi Charles -
>
>Nobody has really addressed the jitter question. It doesn't seem to me
>that
>jitter is directly related to signal loss, regardless of whether the
>loss
>comes from skin effect or the dielectric. But DJ is directly affected
by
>reflections caused by impedance variations, correct? Widening traces
>decreases the impedance variation caused by imperfect etching, which
>could
>decrease DJ. That's my best guess anyway.
>
>Regards,
>Bob Sefton
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
>On
>Behalf Of Grasso, Charles
>Sent: Tuesday, July 05, 2005 11:39 AM
>To: 'si-list@xxxxxxxxxxxxx'
>Subject: [SI-LIST] Q on Trace Width and Jitter for Diff Pairs
>
>Greetings!
>=3D20
>I am stuck on understanding a contradiction - perhaps someone could
>"unstick" me?
>It is understood that (at high frequencies) the dielectric losses in a
>pwb
>dominates the losses of a transmission line. However, I have read in
>various
>publications that increasing the trace widths improves the jitter
>performance of a high speed serial link.
>I would have thought that as a trace width increases the effects of the
>dielectrics would be exacerbated.
>=3D20
>How does increasing the width of a trace improve the DJ of the link?
>=3D20
>Best Regards
>Charles Grasso
>Senior Compliance Engineer
>Echostar Communications Corp.
>Tel:  303-706-5467
>Fax: 303-799-6222
>Cell: 303-204-2974
>Pager/Short Message:  3032042974@xxxxxxxx <mailto:3032042974@xxxxxxxx>
>Email: charles.grasso@xxxxxxxxxxxx;
<mailto:charles.grasso@xxxxxxxxxxxx;>
>Email Alternate: chasgrasso@xxxxxxxx <mailto:chasgrasso@xxxxxxxx>=3D20
>=3D20
>=3D20
>
>
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