Date Index for si-list, 07-2005

[si-list] || [07-2005 Date Index] [07-2005 Thread Index]

[SI-LIST] Agilent TDR Normalization Questions - Eric Bogatin
[SI-LIST] New Packaging SI Opportunity ... - Neeraj Pendse
[SI-LIST] SEU caused by laser illumination - Huiyun Li
[SI-LIST] problems with simulation of loop antenna far field using Wire-MOM - kundanchand chand
[SI-LIST] Isolating feeder cable parasitics in Eye diagram measurement - Jayaprakash
[SI-LIST] Re: SEU caused by laser illumination - steve weir
[SI-LIST] Re: problems with simulation of loop antenna far field using Wire-MOM - Jian-X. Zheng
[SI-LIST] stitching vias - Naren
[SI-LIST] SI/Packaging Posting - Zabinski, Patrick J.
[SI-LIST] Re: stitching vias - Lynne D. Green
[SI-LIST] Re: stitching vias - Chris Padilla (cpad)
[SI-LIST] Paper: Eye Diagrams and BERT for Digital System Interconnect Analysis - Rohan Hubli
[SI-LIST] Re: stitching vias - steve weir
[SI-LIST] Q on Trace Width and Jitter for Diff Pairs - Grasso, Charles
[SI-LIST] Re: Q on Trace Width and Jitter for Diff Pairs - Cosentino, Tony
[SI-LIST] Modeling Connectors and Relays - You, Yang
[SI-LIST] Re: SEU caused by laser illumination - Chris Cheng
[SI-LIST] Re: Q on Trace Width and Jitter for Diff Pairs - Larry Smith
[SI-LIST] Re: Q on Trace Width and Jitter for Diff Pairs - Robert Sefton
[SI-LIST] The effect of temperature on the speed of IC - zhangkun 29902
[SI-LIST] Re: The effect of temperature on the speed of IC - Tom Dagostino
[SI-LIST] Re: The effect of temperature on the speed of IC - Christopher.Jakubiec
[SI-LIST] Chip input capacitance - Edi Fraiman
[SI-LIST] Re: Chip input capacitance - steve weir
[SI-LIST] Re: Q on Trace Width and Jitter for Diff Pairs - Leonard Dieguez
[SI-LIST] Re: Q on Trace Width and Jitter for Diff Pairs - Cuchulain
[SI-LIST] Re: Q on Trace Width and Jitter for Diff Pairs - steve weir
[SI-LIST] AWR SI tools - Zanella, Fabrizio
[SI-LIST] Re: Chip input capacitance - Eugene Mayevskiy
[SI-LIST] power layer question - ma mu
[SI-LIST] Re: Q on Trace Width and Jitter for Diff Pairs - Leonard Dieguez
[SI-LIST] Re: Modeling Connectors and Relays - Zanella, Fabrizio
[SI-LIST] Re: Q on Trace Width and Jitter for Diff Pairs - steve weir
[SI-LIST] Re: power layer question - steve weir
[SI-LIST] Balancing Copper and dielectric losses? - Loyer, Jeff
[SI-LIST] Re: Q on Trace Width and Jitter for Diff Pairs - Leonard Dieguez
[SI-LIST] Re: Balancing Copper and dielectric losses? - steve weir
[SI-LIST] Re: Q on Trace Width and Jitter for Diff Pairs - steve weir
[SI-LIST] Re: Balancing Copper and dielectric losses? - Leonard Dieguez
[SI-LIST] Re: The effect of temperature on the speed of IC - Pramod Parameswaran
[SI-LIST] Re: The effect of temperature on the speed of IC - Yafei Bi
[SI-LIST] Re: SEU caused by laser illumination - Daniel, Erik S., Ph.D.
[SI-LIST] Re: The effect of temperature on the speed of IC - Hui Liu
[SI-LIST] Re: The effect of temperature on the speed of IC - Christopher.Jakubiec
[SI-LIST] scope errors by emi from signal source - Doug Smith
[SI-LIST] Signal Integrity training - Coyle, John [S&FS]
[SI-LIST] EBD in HSPICE - Khan, Mohammad I
[SI-LIST] How to check Capacitance in IBIS model - Yuming Cheng
[SI-LIST] How to create connector's IBIS model from S-Parameters? - Yuming Cheng
[SI-LIST] Impedance deviation due to prepreg shrinking - caydin
[SI-LIST] Re: Impedance deviation due to prepreg shrinking - steve weir
[SI-LIST] Re: EBD in HSPICE - Ray Anderson
[SI-LIST] R: Re: Impedance deviation due to prepreg shrinking - Bleu Carlo Franco
[SI-LIST] Re: R: Re: Impedance deviation due to prepreg shrinking - Robert Haller
[SI-LIST] Re: R: Re: Impedance deviation due to prepreg shrinking - Robert Haller
[SI-LIST] Resistors to use for DDR termination - Dimiter Popoff
[SI-LIST] Re: Resistors to use for DDR termination - Mike Greim
[SI-LIST] Re: Resistors to use for DDR termination - Dimiter Popoff
[SI-LIST] Re: Resistors to use for DDR termination - Scott McMorrow
[SI-LIST] Re: Resistors to use for DDR termination - Novak David (TTE)
[SI-LIST] Re: Resistors to use for DDR termination - Dimiter Popoff
[SI-LIST] Re: Resistors to use for DDR termination - Mikhail Matusov
[SI-LIST] Too much predicted loss - You, Yang
[SI-LIST] Re: Too much predicted loss - Kai Keskinen
[SI-LIST] Re: Resistors to use for DDR termination - Ravinder . Ajmani
[SI-LIST] Re: Resistors to use for DDR termination - Bill Wurst
[SI-LIST] R: Too much predicted loss - Guasti Giovanni
[SI-LIST] Re: si-list Digest V5 #275 - Anders Frederiksen
[SI-LIST] unsubscribe - Vivek-Fpga SHARMA
[SI-LIST] Re: si-list Digest V5 #275 - steve weir
[SI-LIST] Re: Resistors to use for DDR termination - Scott McMorrow
[SI-LIST] Re: R: Too much predicted loss - Istvan novak
[SI-LIST] Re: R: Too much predicted loss - You, Yang
[SI-LIST] DDR-1 termination - Anders Frederiksen
[SI-LIST] Re: R: Too much predicted loss - Mike Greim
[SI-LIST] Re: Too much predicted loss - Scott McMorrow
[SI-LIST] Re: Too much predicted loss - Aubrey_Sparkman
[SI-LIST] Re: Too much predicted loss - Scott McMorrow
[SI-LIST] R: R: Too much predicted loss - Guasti Giovanni
[SI-LIST] Re: R: Too much predicted loss - Loyer, Jeff
[SI-LIST] SI Consultants? - Bob McCreight
[SI-LIST] Re: Signal Integrity training - Hargin, Bill
[SI-LIST] Re: SI Consultants? - Ed Sayre III
[SI-LIST] Re: SI Consultants? - Curt McNamara
[SI-LIST] 4 Ghz PCB - david stern
[SI-LIST] Re: 4 Ghz PCB - Shawn Arnold
[SI-LIST] Re: 4 Ghz PCB - Scott McMorrow
[SI-LIST] About XTK layout file transfer issue - jliou
[SI-LIST] IBIS about differential output - TerenceHsieh
[SI-LIST] Regarding the air gap between via hole and copper - Pang Ning
[SI-LIST] Is there fiberglass in ROGERS material ? - JIA Gongxian
[SI-LIST] R: About XTK layout file transfer issue - Bleu Carlo Franco
[SI-LIST] Re: R: About XTK layout file transfer issue - jliou
[SI-LIST] Re: IBIS about differential output - Beal, Weston
[SI-LIST] Re: R: About XTK layout file transfer issue - Beal, Weston
[SI-LIST] Re: Regarding the air gap between via hole and copper - Dagmara Avanindra
[SI-LIST] Re: Regarding the air gap between via hole and copper - Ken Cantrell
[SI-LIST] Re: Regarding the air gap between via hole and copper - Pang Ning
[SI-LIST] Re: Regarding the air gap between via hole and copper - Pang Ning
[SI-LIST] mvt - Jason
[SI-LIST] Perl scripts for reformatting Touchstone to simple xy table - Cuchulain
[SI-LIST] Make Your Website More Profitable - max
[SI-LIST] Jitter in the output of PLL - Zhangkun
[SI-LIST] SPAM on si-list - Ray Anderson
[SI-LIST] Intel looking for experienced Signal Integrity engineer - Garrison, Gene
[SI-LIST] Mixed Mode S-Parameters and Touchstone Format Files - Ray Anderson
[SI-LIST] DDR Vref Bypassing - Christopher R. Johnson
[SI-LIST] Electrostatic HiZ PCBs - bbolton
[SI-LIST] Re: DDR Vref Bypassing - Tom Dagostino
[SI-LIST] HSPICE and Via Modeling - dav0
[SI-LIST] Field EM Meter - Paradis, Daniel
[SI-LIST] Re: DDR Vref Bypassing - Dale L. Sanders
[SI-LIST] Re: Field EM Meter - Curt McNamara
[SI-LIST] Re: DDR Vref Bypassing - Tom Dagostino
[SI-LIST] Re: HSPICE and Via Modeling - Leonard Dieguez
[SI-LIST] Re: HSPICE and Via Modeling - Chris Cheng
[SI-LIST] Re: HSPICE and Via Modeling - Mirmak, Michael
[SI-LIST] Re: HSPICE and Via Modeling - Chris Cheng
[SI-LIST] Re: HSPICE and Via Modeling - Leonard Dieguez
[SI-LIST] Re: HSPICE and Via Modeling - Ravinder . Ajmani
[SI-LIST] Re: DDR Vref Bypassing - Grasso, Charles
[SI-LIST] Re: HSPICE and Via Modeling - Hargin, Bill
[SI-LIST] Re: DDR Vref Bypassing - Dagmara Avanindra
[SI-LIST] Re: Electrostatic HiZ PCBs - steve weir
[SI-LIST] Re: DDR Vref Bypassing - steve weir
[SI-LIST] Re: Jitter in the output of PLL - steve weir
[SI-LIST] Re: Field EM Meter - Brent DeWitt
[SI-LIST] Re: Electrostatic HiZ PCBs - Brent DeWitt
[SI-LIST] Re: Electrostatic HiZ PCBs - Plesa, James T.
[SI-LIST] unsubscribe - Pfeifer, Alan
[SI-LIST] Re: SPAM: Score 3.9: Re: HSPICE and Via Modeling - dav0
[SI-LIST] Re: via model - Curt McNamara
[SI-LIST] FIR Filter Design - Moeller, Merrick
[SI-LIST] Re: FIR Filter Design - Kuo, Caroline
[SI-LIST] Re: FIR Filter Design - Gary Otonari
[SI-LIST] Re: DDR Vref Bypassing - Bill Wurst
[SI-LIST] Re: DDR Vref Bypassing - Grasso, Charles
[SI-LIST] Re: DDR Vref Bypassing - Bill Wurst
[SI-LIST] Re: DDR Vref Bypassing - Grasso, Charles
[SI-LIST] Re: DDR Vref Bypassing - Christopher R. Johnson
[SI-LIST] Re: DDR Vref Bypassing - Vinu Arumugham
[SI-LIST] Re: DDR Vref Bypassing - Bill Wurst
[SI-LIST] Re: DDR Vref Bypassing - steve weir
[SI-LIST] Re: DDR Vref Bypassing - Bill Wurst
[SI-LIST] Re: DDR Vref Bypassing - sunil.mekad
[SI-LIST] Re: DDR Vref Bypassing - steve weir
[SI-LIST] Re: DDR Vref Bypassing - Grasso, Charles
[SI-LIST] QDR <=> Processor interface - Indira Gazula
[SI-LIST] Re: QDR <=> Processor interface - Dagmara Avanindra
[SI-LIST] Re: QDR <=> Processor interface - Indira Gazula
[SI-LIST] Re: DDR Vref Bypassing - steve weir
[SI-LIST] Re: QDR <=> Processor interface - Dagmara Avanindra
[SI-LIST] Re: DDR Vref Bypassing - Mahabala Shetty
[SI-LIST] Re: DDR Vref Bypassing - Tom Dagostino
[SI-LIST] Re: DDR Vref Bypassing - Juergen Flamm
[SI-LIST] four S channels VNA - Guasti Giovanni
[SI-LIST] Ailtech mauals - KS Lau
[SI-LIST] Re: four S channels VNA - Thomas Beneken
[SI-LIST] Re: four S channels VNA - Thomas Beneken
[SI-LIST] Re: QDR <=> Processor interface - Knut Georg Wiljugrein
[SI-LIST] Re: four S channels VNA - John Fisher (jmfisher)
[SI-LIST] Re: DDR Vref Bypassing - Bill Wurst
[SI-LIST] Re: DDR Vref Bypassing - Chris Cheng
[SI-LIST] Re: DDR Vref Bypassing - steve weir
[SI-LIST] Re: DDR Vref Bypassing - steve weir
[SI-LIST] Re: DDR Vref Bypassing - Vinu Arumugham
[SI-LIST] Re: four S channels VNA - Thomas Beneken
[SI-LIST] DDR Vref Bypassing - Please explain pseudo diff - Grasso, Charles
[SI-LIST] Re: DDR Vref Bypassing - Please explain pseudo diff - Muranyi, Arpad
[SI-LIST] Re: DDR Vref Bypassing - Please explain pseudo diff - Chris Cheng
[SI-LIST] Re: DDR Vref Bypassing - Please explain pseudo diff - Muranyi, Arpad
[SI-LIST] Re: DDR Vref Bypassing - Please explain pseudo diff - Christopher.Jakubiec
[SI-LIST] Re: DDR Vref Bypassing - Please explain pseudo diff - Muranyi, Arpad
[SI-LIST] Re: DDR Vref Bypassing - Please explain pseudo diff - Chris Cheng
[SI-LIST] Re: DDR Vref Bypassing - Please explain pseudo diff - Muranyi, Arpad
[SI-LIST] Re: DDR Vref Bypassing - Please explain pseudo diff - steve weir
[SI-LIST] High speed connector design - Mike Haff
[SI-LIST] solicting articles for Handheld Tester application note - simon zhou
[SI-LIST] 2006 EMC Symposium in Singapore - Li Er Ping
[SI-LIST] subscribe - Neha Arora
[SI-LIST] Differential signal transmission using microstrip cable - 정태식
[SI-LIST] DDRII OCD and ODT - Ken Patterson
[SI-LIST] Re: DDRII OCD and ODT - Ken Cantrell
[SI-LIST] Re: DDR Vref Bypassing - Please explain pseudo diff - Grasso, Charles
[SI-LIST] EMPIRE Software Package Experiences? - You, Yang
[SI-LIST] Re: [IBIS-Users] IBIS Question - seshadri.kirankumar
[SI-LIST] How to use Intel's model? - Yuming Cheng
[SI-LIST] LVTTL SSTL interface - Vicky Kunwar
[SI-LIST] Re: EMPIRE Software Package Experiences? - Thomas Beneken
[SI-LIST] Re: LVTTL SSTL interface - steve weir
[SI-LIST] HSPICE to IBIS - Naren
[SI-LIST] [SI-LIST]network analysis of differential signal using hspice - vani.chandrasekharan
[SI-LIST] Re: LVTTL SSTL interface - Ravinder . Ajmani
[SI-LIST] Re: [SI-LIST]network analysis of differential signal using hspice - Ray Anderson
[SI-LIST] Re: [SI-LIST]network analysis of differential signal using hspice - vani.chandrasekharan
[SI-LIST] Re: HSPICE to IBIS - Abdulrahman Rafiq
[SI-LIST] Re: HSPICE to IBIS - Muranyi, Arpad
[SI-LIST] Re: HSPICE to IBIS - Muranyi, Arpad
[SI-LIST] Re: How to use Intel's model? - Muranyi, Arpad
[SI-LIST] Re: HSPICE to IBIS - Andrew Ingraham
[SI-LIST] Re: HSPICE to IBIS - Lynne D. Green
[SI-LIST] 回复： Re: How to use Intel's model? - Yuming Cheng
[SI-LIST] 回复： Re: How to use Intel's model? - Yuming Cheng
[SI-LIST] ibis models needed - rana sadaf
[SI-LIST] Re: ibis models needed - Kim Helliwell
[SI-LIST] Re: ibis models needed - Syed Huq (shuq)
[SI-LIST] Re: ibis models needed - Abdulrahman Rafiq
[SI-LIST] Re: ??: Re: How to use Intel's model? - Muranyi, Arpad
[SI-LIST] Re: ??: Re: How to use Intel's model? - ariazi
[SI-LIST] differential signaling (common-mode) - Bi Han
[SI-LIST] Re: differential signaling (common-mode) - steve weir
[SI-LIST] 回复： Re: differential signaling (common-mode) - Bi Han
[SI-LIST] Re: 回复： Re: [SI-LIST] differential signal in g (common-mode) - steve weir
[SI-LIST] 回复： Re: differential signaling (common-mode) - Bi Han
[SI-LIST] Re: 回复： Re: [SI-LIST] differential signal in g (common-mode) - steve weir
[SI-LIST] Re: ååï Re: differential signaling (common-mode) - Larry Miller