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Thread Index for si-list, 07-2004

[si-list] || [07-2004 Date Index] [07-2004 Thread Index]

  1. [SI-LIST] Re: si-list Digest V4 #261, Ivan Ndip
  2. [SI-LIST] Ansoft's SI-wave?, Robert Tso
  3. [SI-LIST] Field coupling from an impulse event, Doug Smith
  4. [SI-LIST] High Speed PCB design standards, vishnu.jwalapuram
  5. [SI-LIST] Need to buy standards book or manual, kirana na
  6. [SI-LIST] Re: Need to buy standards book or manual, Geoff Stokes
  7. [SI-LIST] Re: High Speed PCB design standards, Lee Ritchey
  8. [SI-LIST] six layer, eight layer, other, calaf_calaf_calaf
  9. [SI-LIST] Re: Differential pair via modeling, Doug Hopperstad
  10. [SI-LIST] Course on Signal Integrity at San Jose State University, Ji Zheng
  11. [SI-LIST] spliting lvds clk, Moshe Frid
  12. [SI-LIST] Is Impedance Enough for Describing the PDS?, zhangkun 29902
  13. [SI-LIST] Loading IBIS in Signoise!, G.Srinivasan
  14. [SI-LIST] Re: Loading IBIS in Signoise!, Henrik G. Madsen
  15. [SI-LIST] a problem in simulate crystal oscillator, zyq
  16. [SI-LIST] add new power island in a 8 layer stack, calaf_calaf_calaf
  17. [SI-LIST] balun theory, atifshamim khan
  18. [SI-LIST] Re: add new power island in a 8 layer stack, Tom Biggs
  19. [SI-LIST] Re: Is Impedance Enough for Describing the PDS?, Vijay B
  20. [SI-LIST] Re: a problem in simulate crystal oscillator, zyq
  21. [SI-LIST] RMCEMC June presentation download available, Grasso, Charles
  22. [SI-LIST] The future of si-list, Ray Anderson
  23. [SI-LIST] many irregular Tr-Line and smash GND Plane, webhugo
  24. [SI-LIST] Just Testing, Hitendra Patel
  25. [SI-LIST] Re: balun theory, Fasig, Jonathan L.
  26. [SI-LIST] PCB rework speciality houses, Naveen Reddy
  27. [SI-LIST] Vector Fitting Matlab Code Request, sam BB
  28. [SI-LIST] IBIS models for Pb-free (lead-free) BGA package, Giulio Tamberi
  29. [SI-LIST] noise measurement literature, yue xing li
  30. [SI-LIST] why the step should be 0.05ns?, zyq
  31. [SI-LIST] Naveen Reddy, Deac Descoteaux
  32. [SI-LIST] DDR point to point termination, Aric Hadav
  33. [SI-LIST] Re: DDR point to point termination, Landrum, Chris
  34. [SI-LIST] Re: High Speed Termination, Hitendra Patel
  35. [SI-LIST] R: IBIS models for Pb-free (lead-free) BGA package, Giulio Tamberi
  36. [SI-LIST] A question in 2D Extractor & HFSS, yf_xie
  37. [SI-LIST] Automotive ECU EMI problems, Daniel R. Nicoson
  38. [SI-LIST] Re: why the step should be 0.05ns?, zyq
  39. [SI-LIST] Via Impedance!, G.Srinivasan
  40. [SI-LIST] diffusion capacitance measurement, ashvin khole
  41. [SI-LIST] Allegro, pentsapor
  42. [SI-LIST] New 2004 textbook out on high-speed design and signal integrity, Tom Granberg
  43. [SI-LIST] Re: Via Impedance!, Lee Ritchey
  44. [SI-LIST] FW: Allegro, Gary Schneider
  45. [SI-LIST] HSPICE question, Muranyi, Arpad
  46. [SI-LIST] Re: diffusion capacitance measurement, Raymond . Leung
  47. [SI-LIST] Re: Allegro, Crazy Engineer
  48. [SI-LIST] Heatsink acting as EMI shield., Budathoki, Trilok (GE Consumer & Industrial)
  49. [SI-LIST] R: Re: Via Impedance!, Guasti Giovanni
  50. [SI-LIST] Re: Heatsink acting as EMI shield., Zhangkun
  51. [SI-LIST] Can SSTL float?, Peterson, James F (FL51)
  52. [SI-LIST] The function of damping resistor between MCH and DIMM slot, Jie J. Zhou
  53. [SI-LIST] Re: Via modeling & de-embedding, Hassan O. Ali
  54. [SI-LIST] IBIS file data, Pay Chee How
  55. [SI-LIST] Ground bounce, Ramkrishna Reddy
  56. [SI-LIST] Re: Ground bounce, Jim Antonellis
  57. [SI-LIST] 回信： Ground bounce, Jie J. Zhou
  58. [SI-LIST] Hspice with IBIS model containing driver schedule, John Lin (林朝煌)
  59. [SI-LIST] R: Hspice with IBIS model containing driver schedule, Guasti Giovanni
  60. [SI-LIST] Re: Hspice with IBIS model containing driver schedule, Linnenbruegger Dirk
  61. [SI-LIST] Hi,dear all:What's the function of damping resistor between MCH and DIMM slot? Only reduce current?, Jie J. Zhou
  62. [SI-LIST] Dear, can anybody tell me what's the max overshoot and min undershoot value of PCI? thank you!, Jie J. Zhou
  63. [SI-LIST] primary question about spread spectrum clock, zhangkun 29902
  64. [SI-LIST] guard traces (huge), Moshe Frid
  65. [SI-LIST] What is ASTAP?, zhangkun 29902
  66. [SI-LIST] Re: Digest Number 1151, Shalini S
  67. [SI-LIST] Re: guard traces (huge), Budathoki, Trilok (GE Consumer & Industrial)
  68. [SI-LIST] Return path, Budathoki, Trilok (GE Consumer & Industrial)
  69. [SI-LIST] Re: Return path, steve weir
  70. [SI-LIST] How to measure voltage drop on plane, Zhangkun
  71. [SI-LIST] TDR on Package only, Porsh Shih
  72. [SI-LIST] Re: How to measure voltage drop on plane, zhangkun 29902
  73. [SI-LIST] IBIS Open_source and ECL models, Xiaoling Huang
  74. [SI-LIST] 回信： How to measure voltage drop on plane, Jie J. Zhou
  75. [SI-LIST] (no subject), Ritika DUA
  76. [SI-LIST] PCI, Ritika DUA
  77. [SI-LIST] SSTL Standard, Ritika DUA
  78. [SI-LIST] LVTTL to CML, Jonathan Swift
  79. [SI-LIST] the relation between speed grade and rising time of altera fpga devices, Jerry John
  80. [SI-LIST] Low noise electronics and Xilinx high-speed links, Andreas Kaeufl
  81. [SI-LIST] question regarding Ansoft Maxwell 2D repetitive simulations, ayhz2003
  82. [SI-LIST] Re: question regarding Ansoft Maxwell 2D repetitive simulations, Aubrey_Sparkman
  83. [SI-LIST] The precision of Ansoft Maxwell 2D, zhangkun 29902
  84. [SI-LIST] Re: The precision of Ansoft Maxwell 2D, zhangkun 29902
  85. [SI-LIST] How to interpret Jitter Specification, Bashir, Shiraz (MED)
  86. [SI-LIST] Re: How to interpret Jitter Specification, steve weir
  87. [SI-LIST] ECL model, Xiaoling Huang
  88. [SI-LIST] LVTTL to HSTL, kbkrishnan
  89. [SI-LIST] Re: EMI simulation tools, 'Ron Matthews'
  90. [SI-LIST] Hi,all. How can we do if DDRI and DDR2 are laid in the same trace? How to deal with the termination? thanks!, Jie J. Zhou
  91. [SI-LIST] xtk application crashes, BRanjul
  92. [SI-LIST] Re: xtk application crashes, Hargin, Bill
  93. [SI-LIST] SPICE for LINUX, sivi.cla@xxxxxxxxx
  94. [SI-LIST] skin effect, Santhosh E P (setavala)
  95. [SI-LIST] Re: skin effect, Dunbar, Tony
  96. [SI-LIST], Yee Chung
  97. [SI-LIST] Smart Voltage Regulator for PCI Card, Nitin Sood
  98. [SI-LIST] SI Simulation of GHz signals, Clifford van Dyk
  99. [SI-LIST] Sr. Signal Integrity Engineer opportunity, James L. Fitzpatrick
  100. [SI-LIST] Re: SI Simulation of GHz signals, Julian Ferry
  101. [SI-LIST] series resistor on SSTL-2, Leong
  102. [SI-LIST] Manipulation of ICM and/or ICEM model in EDA tool, Sogo Hsu
  103. [SI-LIST] DRAM Address lines : Daisy Chain or "T"?, SEOW, ERWIN
  104. [SI-LIST] Re: DRAM Address lines : Daisy Chain or "T"?, steve weir
  105. [SI-LIST] Oscilloscope probe modeling, Amir Pinhasovich
  106. [SI-LIST] Re: series resistor on SSTL-2, Peterson, James F (FL51)
  107. [SI-LIST] SDRAM output impedance, Leong
  108. [SI-LIST] DDR Eye diagrams, Novak David
  109. [SI-LIST] Re: DDR Eye diagrams, ji-wei_du
  110. [SI-LIST] AW: DDR Eye diagrams, hermann.ruckerbauer
  111. [SI-LIST] Re: AW: DDR Eye diagrams, ji-wei_du
  112. [SI-LIST] AW: AW: DDR Eye diagrams, hermann.ruckerbauer
  113. [SI-LIST] Drivers on a 50Ohm line, Bhagwath, Nitin
  114. [SI-LIST] Re: Drivers on a 50Ohm line, steve weir
  115. [SI-LIST] Re: si-list: clifford@blackhole.net post needs approval, Ray Anderson
  116. [SI-LIST] resitor packs vs networks in DDR design, Alex Jose
  117. [SI-LIST] Subject: SI Simulation of GHz signals_28Jul04, Ekkehard Miersch
  118. [SI-LIST] DDR DRAM, Landrum, Chris
  119. [SI-LIST] Re: DDR DRAM, Landrum, Chris
  120. [SI-LIST] DesignCon 2005 call for papers, Zhiping Yang
  121. [SI-LIST] Fwd: Re: Re: Drivers on a 50Ohm line, Dav0 Lieby
  122. [SI-LIST] Announcement: Mayo EM Solver Software Available, Techentin, Robert W.
  123. [SI-LIST] about XAUI error, myan
  124. [SI-LIST] Andreas Graevinghoff/DE/ETAS is out of office., Andreas . Graevinghoff
  125. [SI-LIST] Re: about XAUI error, steve weir
  126. [SI-LIST] Re: si-list Digest V4 #302, Rajesh NARWAL



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