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[SI-LIST] Re: DDR point to point termination
- From: "Gil Gafni" <gil.gafni@xxxxxxxx>
- To: <james.f.peterson@xxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Tue, 13 Jul 2004 15:07:52 -0700
Hi Jim et al
Here are my 2 cents
On another design we had about 7 inch traces for the data (point to
point). We figured that the capacitance of the line (roughly 3pF per
inch times 7 is about 20pF) will be enough for the bus turnaround (when
both ends are high Z), so we eliminated the pull ups (saves on parts,
power consumption, and eases the layout) on the first design we had
series termination at both ends. We later learned that one of the sides
has a weaker driver, so we changed the 33ohm series termination to a
0ohm, and it worked. In the last version we changed the memories, and
some has the ability to control the strength of the buffer, so we used
the low power, and again we realized that we can spare the series
termination, though we decided to keep it.
Gil
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Peterson, James F (FL51)
Sent: Tuesday, July 13, 2004 10:20 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: DDR point to point termination
maybe it's 4 devices because of data width not depth...
I am also interested in DDR SSTL term schemes. I am simulating a point
to point architecture with no pull-ups in the interface. I am assuming a
longer run than 2 inches. More like 6 inches. the data bus is
bi-directional so i have a series terminating resistor at both drivers.
This seems to be very effective. The recommended pull-up adds no
benefit, and adds to the power so I don't plan on using it. The catch,
though, is to make sure the bus doesn't tri-state, cause it'll float w/o
the pull-up.
jim peterson
honeywell
-----Original Message-----
From: Landrum, Chris [mailto:chris_landrum@xxxxxxxxxx]
Sent: Tuesday, July 13, 2004 1:02 PM
To: arich1970@xxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: DDR point to point termination
I have implemented a point to point DDR interface (200MHz) using series
resistors located in the middle of the data traces. I have seen the
same app note you speak of requiring the trace lengths to be less than
2in, which seems to work well in my application. =20
However, you describe a DDR interface consisting of 4 devices. This is
not point-to-point as the devices will share data lines. This interface
should be simulated.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Aric Hadav
Sent: Tuesday, July 13, 2004 11:24 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] DDR point to point termination
Hi,
I'm designing an embedded system with DDR. I'm using a CPU connected to
an=20 on board four 16 bit DDR devices (no DIMM). I have 2 questions
though - 1. can I use only a series termination on the data bus (I saw a
few AN that=20 state that if the disctance between the controller and
the DDR IC's is upto=20 2" its ok). has anyone did it with a 200MHz
clock ? 2. since the address and control lines operate in half the data
rate and the=20 DDR controller is very lightly loaded (only 4 chips)
can I use only series=20 termination for address and control ? has
anyone did it with good resaults ?
thanks,
Aric
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=20
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