FreeLists / si-list / [SI-LIST] Re: spliting lvds clk

[steve weir <weirsp@xxxxxxxxxx>]

Moshe, the right answer depends.  Assuming that the distance difference is 
not so much as to create a timing problem of its own due to differences 
between clock and data physical lengths, then end terminate at the far FPGA.

With that said, 800MHz for the basic clock rate is pretty marginal for a 
common clocked bus with FPGAs.  If the FPGA design does not have a phase 
adjustment mechanism it is very unlikely to work reliably under any 
circumstances with any current production FPGAs.  Current generation FPGAs 
are only really able to trim phase to a resolution of about 250ps, and burn 
up considerable resources doing so.  The design engineer has some homework 
to do.

Steve.
At 10:42 AM 7/7/2004 +0200, Moshe Frid wrote:
>hi all
>
>I need to split diff clk of lvds at 800 MHz to 2 fpga that are far one
>from the other
>the data are in 8 channels ,4 to each fpga .
>should I split them with buffers ?   what about the delay of the clk
>(the data would not be buffered)
>
>tnks.
>
>Moshe Frid
>Adcom pcb design
>
>Email:moshef@xxxxxxxxxxx
>
>
>
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