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Thread Index for si-list, 07-2003

[si-list] || [07-2003 Date Index] [07-2003 Thread Index]

  1. [SI-LIST] need advice on books, karan bagga
  2. [SI-LIST] Re: how to model an oscillator ?, Ingraham, Andrew
  3. [SI-LIST] How to control CMOS circuit¡¯s stage-stage DC bias voltage variation with process variation?, Bi Han
  4. [SI-LIST] IBIS Interconnect Modeling Specification - Request for Feedback, Mirmak, Michael
  5. [SI-LIST] via teardropping effect on signal integrity?, Ivor Bowden
  6. [SI-LIST] Re: via teardropping effect on signal integrity?, Pat Diao
  7. [SI-LIST] resistor array compact PCI signals, Nico Fleurinck
  8. [SI-LIST] rapid io tracking/termination impedance, WALKER, Mark
  9. [SI-LIST] SPI-4 interface, Patrick Jabbaz
  10. [SI-LIST] Re: SPI-4 interface, Tom Biggs
  11. [SI-LIST] Re: resistor array compact PCI signals, Richard . Litt
  12. [SI-LIST] measuring internal signals on a chip, Doug Smith
  13. [SI-LIST] 8 Layer stack up, Nagaraj
  14. [SI-LIST] Inclusion of RLGC package info in IBIS, R, Granthana
  15. [SI-LIST] Re: 8 Layer stack up, Ravinder . Ajmani
  16. [SI-LIST] Marshall Sherfield Fellowship, lin shen
  17. [SI-LIST] si-list is back in business, Ray Anderson
  18. [SI-LIST] Differential bus emission, Dorin
  19. [SI-LIST] Re: Differential bus emission, Lee Ritchey
  20. [SI-LIST] [Freelists News] crippling outage, partial recovery, Ray Anderson
  21. [SI-LIST] How many Ground pins are enough, Ravinder . Ajmani
  22. [SI-LIST] Field Solver Questions, Sainath Nimmagadda
  23. [SI-LIST] Re: Regulatory testing, Lfresearch
  24. [SI-LIST] Fwd: vgs stress in digital cmos process, Bi Han
  25. [SI-LIST] IBIS models for RC Network, Suresh.K
  26. [SI-LIST] Re: si-list Digest V3 #186, Thomas Beneken
  27. [SI-LIST] Recommendation for high-speed digital input protection?, JP Nicholls
  28. [SI-LIST] Re: Recommendation for high-speed digital input protection?, Tom Biggs
  29. [SI-LIST] Re: Fwd: vgs stress in digital cmos process, Christopher Jakubiec
  30. [SI-LIST] Re: LVDS Routing, Gupta, Deepali
  31. [SI-LIST] Free webinar on translating SPICE models to IBIS, Lynne Green
  32. [SI-LIST] Crystal Oscillator, pankaj kumar
  33. [SI-LIST] Measuring Crosstalk, chandaharitha
  34. [SI-LIST] paper on 9ps high-resolution TDR, Schoen, Kipp
  35. [SI-LIST] Question on DDR SDAM timing spec, Chris Cheng
  36. [SI-LIST] Lumped Vs Distributed Model, chandaharitha
  37. [SI-LIST] can a open drain pin drive high impedance?, hariharan
  38. [SI-LIST] AW: Question on DDR SDAM timing spec, hermann . ruckerbauer
  39. [SI-LIST] what is the max trace length for the signals adjecent to the power planes., Pushpraj Adhage
  40. [SI-LIST] Via anti-pad on 2G signaling, chris . mcgrath
  41. [SI-LIST] FW: Field Solver Questions, Sainath Nimmagadda
  42. [SI-LIST] Re: Question on DDR SDAM timing spec, Chris Cheng
  43. [SI-LIST] Re: Reducing SSO noise in an FPGA, bpanos
  44. [SI-LIST] [Fwd: Re: Re: Reducing SSO noise in an FPGA], Scott McMorrow
  45. [SI-LIST] Drivers-Receivers in DSM technologies, manthos labropoulos
  46. [SI-LIST] Need Signal Integrity engineer ASAP, Kevin Pierpoint
  47. [SI-LIST] Re: Differential traces in ebd file, Muranyi, Arpad
  48. [SI-LIST] DESIGNCON 2004 CALL FOR PAPERS, Ozgur Misman
  49. [SI-LIST] extraction tool, houfei chen
  50. [SI-LIST] IEEE CPMT Society Phoenix Chapter - Aug 2003 meeting announcement, Sam Karikalan
  51. [SI-LIST] RMCEMC July meeting announcement, Charles Grasso
  52. [SI-LIST] AIC7899 pci SCSI controller, karan bagga
  53. [SI-LIST] op-amp compensation capacitor in digital cmos process, Bi Han
  54. [SI-LIST] topology for memory bus, karan bagga
  55. [SI-LIST] Re: op-amp compensation capacitor in digital cmos process, Bill . Cohen
  56. [SI-LIST] Job Opening, Pete Deyring
  57. [SI-LIST] HyperlynxSI issue, Santhosh E P
  58. [SI-LIST] ibis in hspice, =?big5?b?U3RhbmxleS5DaGl1KKr0q6uyTSk=?=
  59. [SI-LIST] R: ibis in hspice, Guasti Giovanni
  60. [SI-LIST] PCI-Express System Level Trace Impedance Value, Chan, Michael (Eng Hou)
  61. [SI-LIST] Re: PCI-Express System Level Trace Impedance Value, Coleman, Dave
  62. [SI-LIST] R: PCI-Express System Level Trace Impedance Value, Guasti Giovanni
  63. [SI-LIST] Microstrip Inductance, Sainath Nimmagadda
  64. [SI-LIST] Re: HyperlynxSI issue, Angulo, John
  65. [SI-LIST] Re: si-list Digest V3 #194, Thomas Beneken
  66. [SI-LIST] Battery model, JP
  67. [SI-LIST] Any good document for DC offset compensation?, Bi Han
  68. [SI-LIST] Distant Reference Planes Through Other Planes, Brown, William G
  69. [SI-LIST] Help!, wgf218
  70. [SI-LIST] spice to ibis, karan bagga
  71. [SI-LIST] Finding Er (Permitivity), Kamal EC
  72. [SI-LIST] Re: Finding Er (Permitivity), Clewell, Craig
  73. [SI-LIST] 2.5Gbps, Dorin
  74. [SI-LIST] Re: 2.5Gbps, Zabinski, Patrick J.
  75. [SI-LIST] Re: Recommendation for high-speed digital inputprotection?, Roman PRAGER
  76. [SI-LIST] LICA caps?, Fasig, Jonathan L.
  77. [SI-LIST] Re: LICA caps?, Istvan Novak - Board Design Technology
  78. [SI-LIST] Re: Inductance vs. Impedance, andrew . c . byers
  79. [SI-LIST] FPGA interface with PS/2 Mouse, Adeel Malik
  80. [SI-LIST] Re: Recommendation for high-speed digital input pro tection?, Geoff Stokes
  81. [SI-LIST] Tpd Spreadsheet uploaded to si-list web file archives, Ray Anderson
  82. [SI-LIST] Behavioral modeling, Panch Chandrasekaran
  83. [SI-LIST] Re: Behavioral modeling, Muranyi, Arpad
  84. [SI-LIST] 2.5 D numerical softwares, haowang
  85. [SI-LIST] More jobs at Sigrity!, Teo Yatman
  86. [SI-LIST] Re: PCB signal speed over temperature, Song, Wil Choon
  87. [SI-LIST] Re: si-list Digest V3 #200, Thomas Beneken
  88. [SI-LIST] Re: 2.5 D numerical softwares, Swanson, Dan
  89. [SI-LIST] Re: Tpd Spreadsheet uploaded to si-list web file archives, Ray Anderson
  90. [SI-LIST] AW: Re: PCB signal speed over temperature, mathias . borcke
  91. [SI-LIST] Resource for Equivlent Circuit Models, Moeller, Merrick
  92. [SI-LIST] Capacitor ESR, mappiani
  93. [SI-LIST] Re: Resource for Equivlent Circuit Models, Ray Anderson
  94. [SI-LIST] Re: Distant Reference Planes Through Other Planes, Brown, William G
  95. [SI-LIST] SPICE to IBIS Methodology webinar, Lynne Green
  96. [SI-LIST] Why we need to add input buffer for RF amplifier?, Bi Han
  97. [SI-LIST] Cadence Schematic File, Arshad Suhail Farooqui
  98. [SI-LIST] Re: PCB signal speed over temperature (and finding Er), Song, Wil Choon
  99. [SI-LIST] gnd plane kept close to track, karan bagga
  100. [SI-LIST] MOS cap on chip for DECOUPLING, Bi Han
  101. [SI-LIST] trace delay/inch, Santhosh E P
  102. [SI-LIST] Re: MOS cap on chip for DECOUPLING, Rajat Chauhan
  103. [SI-LIST] Re: gnd plane kept close to track, Geoff Stokes
  104. [SI-LIST] PCI-Express Clarifications., Rahul R
  105. [SI-LIST] Hi, kirana na
  106. [SI-LIST] Calculate Driver Impedance from IBIS, Miltos Dalakidis
  107. [SI-LIST] Please turn off your account when OOP, Loyer, Jeff
  108. [SI-LIST] Re: Please turn off your account when OOP, Matthew Humphreys
  109. (no subject), Kirti Barpande
  110. [SI-LIST] Reduce the slew rate of a driver, Nelson Rasquinha
  111. [SI-LIST] Mentor Hyperlinx ?, Joel Brown
  112. [SI-LIST] Re: Mentor Hyperlinx ?, Joel Brown
  113. [SI-LIST] how to measure the coupling effect of the coupled lines with vector network analyzer, Liu Ye
  114. [SI-LIST] MECL, karan bagga
  115. [SI-LIST] Fwd: Re: si-list Digest V3 #194, Sainath Nimmagadda
  116. [SI-LIST] 答复: Re: how to measure the coupling effect of the coupled lines with vector network analyzer, ji-wei_du
  117. [SI-LIST] Antw: MECL, Robert Nowak
  118. [SI-LIST] Re: how to measure the coupling effect of the coupled lines with vector network analyzer, Guasti Giovanni
  119. [SI-LIST] Power planes, karan bagga
  120. [SI-LIST] Re: MECL, Geoff Stokes
  121. [SI-LIST] pl. comment on my stack up, karan bagga
  122. [SI-LIST] How to calculate output impedance?, Pfeifer, Alan
  123. [SI-LIST] Re: Power planes, Ray Anderson
  124. [SI-LIST] AGTL, Raymond Langlois
  125. [SI-LIST] Re: Fwd: Re: si-list Digest V3 #194, Sainath Nimmagadda
  126. [SI-LIST] HS Ground and Power ground seperation, Tabatchnick, Justin
  127. [SI-LIST] A general question of -48V power supply, 宜帆
  128. [SI-LIST] Re: HS Ground and Power ground seperation, christopher . heard
  129. [SI-LIST] Re: A general question of -48V power supply, Nagel, Michael
  130. [SI-LIST] Cadstar SI & Zuken Hot Stage, Paul Bicknell
  131. [SI-LIST] Re: Cadstar SI & Zuken Hot Stage, Ram Ram Ram
  132. [SI-LIST] SPICE Tools, Moeller, Merrick
  133. [SI-LIST] Crystal modelling parameters and parallel resonance frequency formula, Jean_Pierre . Bouthemy
  134. [SI-LIST] PSPICE to HSPICE, Kuan-Wei Wu
  135. [SI-LIST] Re: Crystal modelling parameters and parallel resonance frequency formula, Ray Anderson
  136. [SI-LIST] OOP problem, changing Reply-To header, Matthias Weingart
  137. [SI-LIST] Re: OOP problem, changing Reply-To header, art_porter
  138. [SI-LIST] Conversion from dB to ohm, Bob Patel
  139. [SI-LIST] Re: Conversion from dB to ohm, Larry Barnes
  140. [SI-LIST] Re: Crystal Oscillator, Ray Anderson
  141. [SI-LIST] CPWG, Bob Patel
  142. [SI-LIST] pwr/ground, Ted Leyes
  143. [SI-LIST] least inductance path(return current), karan bagga
  144. [SI-LIST] HSPICE Control options for crystal simulations, Yehuda Yizraeli
  145. [SI-LIST] Presentation on new pcb reference designs and models, Julian Ferry
  146. [SI-LIST] New SI jobs at Sigrity, Teo Yatman
  147. [SI-LIST] Microstrip Inductance (Old Wine in New Bottle), Dr. Sainath Nimmagadda
  148. [SI-LIST] Re: Microstrip Inductance (Old Wine in New Bottle), Ed Priest
  149. [SI-LIST] Tantalum chip capacitors in CPCI Platform!, Avi Hayun
  150. [SI-LIST] Capacitors and Anti-resonance, Paradis, Daniel
  151. [SI-LIST] Re: Capacitors and Anti-resonance, Istvan Novak - Board Design Technology
  152. [SI-LIST] Losses - 2.5Gbps on FR4, Dorin
  153. [SI-LIST] Re: Losses - 2.5Gbps on FR4, Geoff Stokes
  154. [SI-LIST] This is a test OOP, Ray Anderson
  155. [SI-LIST] Anti Vacation Message Grand Experiment, Ray Anderson
  156. [SI-LIST] Re: Anti Vacation Message Grand Experiment, Atul Rastogi
  157. [SI-LIST] Bart Bouma/RMD/PHYCOMP/YAGEO is out of the office., Bart Bouma
  158. [SI-LIST] Re: What is OO'P'?, ikanno
  159. [SI-LIST] Antw: Re: Capacitors and Anti-resonance, Robert Nowak
  160. [SI-LIST] threshold, hariharan
  161. [SI-LIST] QDRII FPGA design, Chris Betz
  162. [SI-LIST] Re: threshold, Clewell, Craig
  163. [SI-LIST] TDR Transform, Moeller, Merrick
  164. [SI-LIST] si-list experiment, Ray Anderson
  165. [SI-LIST] Autoreply:, Ray Anderson
  166. [SI-LIST] Out of Office AutoReply:, Ray Anderson
  167. [SI-LIST] High Speed Design Books.., Rahul R
  168. [SI-LIST] Re: High Speed Design Books.., Hossain, Mohammed M
  169. [SI-LIST] More High Speed Design Books, mmunroe
  170. [SI-LIST] Re: CPWG, D G
  171. [SI-LIST] Re: TDR Transform, D G
  172. [SI-LIST] Quasi Static Assumptions, Moeller, Merrick
  173. [SI-LIST] Re: Quasi Static Assumptions, Hassan O. Ali
  174. [SI-LIST] UltraCAD ESR and Bypass Capacitor Caculator, Abe Riazi
  175. [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator, Abe Riazi
  176. [SI-LIST] IBIS packaging models, Russell Rapport



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