FreeLists / si-list / [SI-LIST] Re: Reducing SSO noise in an FPGA

[bpanos <bill.panos@xxxxxxxxxxxxxxx>]

Education..yes, well, I'm sure we all need to be educated (english or
otherwise). I suppose if we knew everything,  we could forgo writing e-mails to
the SI-list...
My experience with putting BC in an application involving SSO in null. If we all
state that SSO is strictly a die problem, then there is nothing BC can do.
As for pwr bounce, how about a 5Ghz signal + 3rd harmonic (@15 GHz)  emanating
from an ASIC TX line that has coupled to pwr (via a "via"). But as you stated
before if we judiciously place our reference planes within the PCB, this should
never happen! At this point, I think we've sufficiently beat a dead horse...I'm
moving on
Cheers

-Bill





Chris Cheng wrote:

> Guest or guess BC is still useless for solving SSO problem. The vddo or vsso
> noise that developed at the source of the driver is way too far for anything
> except on die or package decoupling to be effective. I've done plenty of
> modeling and simulations with on die, package (flip chip or wire bond) and
> board model and real measurement to convince myself. There is no debate. BC
> is useless for solving SSO noise problem if the signals are properly
> referenced.
> On the other hand, I will be interested to find out what you have done to
> disagree with me. Let's share your experiences.
> As for your comments about using BC for SSO noise due to supply bounce. I
> would love to know what kind of power supply would generate noise with
> frequency so high that regular bypass cap ESL is too high to decouple.
> I guest (oops guess) I need to be educated.
>
> -----Original Message-----
> From: bpanos [mailto:bill.panos@xxxxxxxxxxxxxxx]
> Sent: Friday, July 11, 2003 3:26 PM
> To: Chris Cheng
> Cc: si-list@xxxxxxxxxxxxx
> Subject: Re: [SI-LIST] Re: Reducing SSO noise in an FPGA
>
> Chris
> I think it's "guest" not "guess", (might want to check your syntax)
> I disagree with your notion that BC is useless in an SSO applications, Even
> with
> as you say with good reference pane placement. SSO problems may be
> manifested by
> supply bounce or ground. Concerning supply bounce in the presence of bypass
> caps
> and issues with ESL (low ESL caps are not always provided or an option), BC
> could be entertained. To what degree BC would be of a benefit is up to
> debate.
>
> Bill
>
> Chris Cheng wrote:
>
> > BC is useless to solve packaging SSO or any SSO problem for that matter if
> > you manage your signal reference plane correctly on the PCB. If you choose
> > to use the wrong reference plane for your I/O and then decided to throw
> > money to fix it with BC, be my guess.
> >
> > Chris
> >
> > -----Original Message-----
> > From: bpanos [mailto:bill.panos@xxxxxxxxxxxxxxx]
> > Sent: Friday, June 27, 2003 4:05 PM
> > To: perry.qu@xxxxxxxxxxx
> > Cc: zhang_kun@xxxxxxxxxx; fzanella@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] Re: Reducing SSO noise in an FPGA
> >
> > I personally have not tried implementing this particular application, in
> > this fashion, but I wonder how well using BC (buried capacitance) material
> > would work with SSO issues with an FPGA.
> > Granted, there may not be enough capacitance / sq, though with 0.5mil BC
> it
> > might be an option..
> > Regards,
> > Bill
> >
> > Perry Qu wrote:
> >
> > > Hi, Zhangkun:
> > >
> > > We have been using 100nF cap extensively in our high speed design (>
> > 100MHz) and so far so good. In my understanding, small ESL is the key to
> > make a flat impedance curve in frequency
> > > range, as explained here many times by Larry Smith and Istvan Novak.
> Small
> > caps such as NPO 1nF will normally give us  high Q since resonance factor
> > increase when ESL increase, and when
> > > ESR and C decrease. For NPO cap, it has very small ESR and small C, so
> if
> > we do not control ESL to very small value, we will end up with high Q.
> Such
> > high Q cap may cause strong
> > > anti-resonance when mixed with other cap and/or plane pairs. In our
> > designs, since we can't control ESL very well with special
> stackup/routing,
> > we use 1nF very carefully.
> > >
> > > Regards
> > >
> > > Perry
> > >
> > > Zhangkun wrote:
> > >
> > > > Dear Zanella
> > > >
> > > > I think 0.1uF and 0.22uF is too large for decoupling. When the
> frequency
> > goes up to 100MHz, these two kind of caps will be of no use. Istvan has
> > writen one paper about measuring caps.
> > > >
> > > > Best Regards
> > > >
> > > > Zhangkun
> > > > 2003.06.26
> > > > ----- Original Message -----
> > > > From: "Fabrizio Zanella" <fzanella@xxxxxxxxxxxx>
> > > > To: <si-list@xxxxxxxxxxxxx>
> > > > Sent: Thursday, June 26, 2003 12:01 AM
> > > > Subject: [SI-LIST] Reducing SSO noise in an FPGA
> > > >
> > > > > I would like to hear about experiences regarding methods of reducing
> > > > > simultaneous switching noise in a large FPGA, BGA package.  Let's
> > assume
> > > > > a 128bit bus, with a signal frequency of 100MHz.
> > > > > How effective is adding ground planes 2 mils from the VCC planes in
> > > > > reducing SSN? If one uses BC, does every VCC pin in the FPGA require
> > > > > decoupling? And should the caps be tied to the BGA pins with blind
> > vias
> > > > > so they can be placed directly under the BGA?  What are the optimal
> > > > > values for the decoupling capacitors, 0.1uf, 0.22uF?
> > > > >
> > > > > Thanks very much and regards,
> > > > >
> > > > >
> > > > > Fabrizio Zanella
> > > > > Principal Hardware Design Engineer
> > > > > Broadbus Technologies
> > > > > fzanella@xxxxxxxxxxxx
> > > > > =20
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> > >
> > > --
> > > Perry Qu
> > >
> > > Design & Qualification       |      600 March Road
> > > Alcatel Canada               |      Ottawa, ON K2K 2E6, Canada
> > >
> > > DID: (613) 7846720           |      FAX: (613) 5993642
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