FreeLists / si-list / [SI-LIST] Re: Question on DDR SDAM timing spec

[Chris Cheng <chris.cheng@xxxxxxxxxxxx>]

Hermann,

That's it. tWRRES is the limiting width parameter not tWPRE. But it =
seems
tWPRES,tCLmin and tDQSSmin implies tWPRE (except the very tiny -5%tCK =
in
tCLmin)? Why does one need to spec out tWPRE then ?

Jonathan,

If you believe in Hermann's comment, 1/2tCK preamble is still going to
violate tWPRES in case of tDQSSmax. You will need at least 3/4tCK =
preamble.
I think that is one of the reason why the Read preamble tRPRE has been
extended to 0.9tCKmin. All these limits convince me not to source the =
DIMM
clock from the memory controller. While it makes your life easy for the
tDQSS during write, you pay it back in DQS skew in read.

Good discussion.
Chris

-----Original Message-----
From: hermann.ruckerbauer@xxxxxxxxxxxx
[mailto:hermann.ruckerbauer@xxxxxxxxxxxx]
Sent: Friday, July 11, 2003 1:11 AM
To: chris.cheng@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: AW: [SI-LIST] Question on DDR SDAM timing spec


Hi Chis,

there is one more parameter, that would not be fullfilled in your case:
tWPRES=20

This parameter prohibits a late write with a short preamble, and is =
measured
from the falling edge of the clock with a value of 0!

regards

Hermann

-----Urspr=FCngliche Nachricht-----
Von: Chris Cheng [mailto:chris.cheng@xxxxxxxxxxxx]=20
Gesendet: Freitag, 11. Juli 2003 01:57
An: si-list@xxxxxxxxxxxxx
Betreff: [SI-LIST] Question on DDR SDAM timing spec


Hi there,

I am a little confused in the JEDEC DDR SDRAM timing spec and some of =
its
electrical implications.

Here's my original thought :
1) During bus idle the SSTL_2 input level will be floating round vddq/2
2) DQS receivers do not like input level being vddq/2, it will either
oscillate or sense an incorrect logic level. Either the receivers have =
to be
disabled or data that gets clocked in has to be discarded
3) DDR DRAM spec uses tDQSS to defined the absolute arrive time of DQS
w.r.t. the DRAM input ck/ck#. It can arrive as late as 1.25tCK or as =
early
as 0.75tCK.
4) DRAM control logic has to assume the DQS within this time is valid
5) However, the preamble time for write tWPRE only requires the DQS to =
be
parked to low level at a minimum of 0.25tCK before the first rising =
edge of
tDQS.
6) This means, in a limiting case, a memory controller can send the DQS =
to
the target DRAM as late as 1.25tCK (maybe due to heavy loading, DRAM =
clock
being too early etc) while keeping the bus floating all the way till =
1.00tCK
(thus meeting the 0.25tCK tWPRE requirement).=20
7) However, the poor DRAM DQS receiver has to assume anything arrive =
after
0.75tCK as valid strobe signal. Thus between 0.75-1tCK, the DQS input =
is
floating at VDDQ/2 and god knows what kind of glitch exist at the =
output of
the DQS receiver that will be used to latch in garbage/extra data.

I am sure a lot of smart people come out with this spec and I make a =
mistake
somewhere in this argument. Can someone point it out to me ? Thanks in
advanced, Chris

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