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[SI-LIST] Re: Question on DDR SDAM timing spec
- From: Steve Horne <sch@xxxxxxxxxxxxxx>
- To: chris.cheng@xxxxxxxxxxxx
- Date: Fri, 11 Jul 2003 08:49:14 -0500
You are correct that the DQS signal needs to be ignored except
when it is expected to have valid transitions. The read preamble
time gives you some time to sort of enable the DQS sensing logic.
Then you have to know when the last transition has occurred so
that you ignore DQS again (so you don't accidentally capture junk
at the end of the burst).
Steve
Chris Cheng writes:
> Hi there,
>
> I am a little confused in the JEDEC DDR SDRAM timing spec and some of its
> electrical implications.
>
> Here's my original thought :
> 1) During bus idle the SSTL_2 input level will be floating round vddq/2
> 2) DQS receivers do not like input level being vddq/2, it will either
> oscillate or sense an incorrect logic level. Either the receivers have to be
> disabled or data that gets clocked in has to be discarded
> 3) DDR DRAM spec uses tDQSS to defined the absolute arrive time of DQS
> w.r.t. the DRAM input ck/ck#. It can arrive as late as 1.25tCK or as early
> as 0.75tCK.
> 4) DRAM control logic has to assume the DQS within this time is valid
> 5) However, the preamble time for write tWPRE only requires the DQS to be
> parked to low level at a minimum of 0.25tCK before the first rising edge of
> tDQS.
> 6) This means, in a limiting case, a memory controller can send the DQS to
> the target DRAM as late as 1.25tCK (maybe due to heavy loading, DRAM clock
> being too early etc) while keeping the bus floating all the way till 1.00tCK
> (thus meeting the 0.25tCK tWPRE requirement).
> 7) However, the poor DRAM DQS receiver has to assume anything arrive after
> 0.75tCK as valid strobe signal. Thus between 0.75-1tCK, the DQS input is
> floating at VDDQ/2 and god knows what kind of glitch exist at the output of
> the DQS receiver that will be used to latch in garbage/extra data.
>
> I am sure a lot of smart people come out with this spec and I make a mistake
> somewhere in this argument. Can someone point it out to me ?
> Thanks in advanced,
> Chris
>
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