FreeLists / si-list / [SI-LIST] Fwd: vgs stress in digital cmos process

[si-list] || [Date Prev] [07-2003 Date Index] [Date Next] || [Thread Prev] [07-2003 Thread Index] [Thread Next]

[SI-LIST] Fwd: vgs stress in digital cmos process

From: Bi Han <mike_bihan@xxxxxxxxxxxx>
To: List` Si <si-list@xxxxxxxxxxxxx>
Date: Thu, 10 Jul 2003 08:23:53 +0800 (CST)

HI, experts:
 
I want to know that in 0.18um Digital CMOS process, major stress concern is Vgs 
or Vds?
 
i.e., if 1.8v NMOS's Vgs is higher than 1.8v, such as 1.9 or 2.2, will that 
cause reliability problem?
 
According to one paper, only Vds higher than 1.8v will cause reliability issue. 
The margin for Vgs will be much higher.
 
Can any people familiar with silicon explain it for me? TSMC data may be used 
for reference.
 
Thanks!
 
BH
(If you have received , please ignore, thanks)







---------------------------------
Do You Yahoo!?
¹úÄÚµçÓÊÓÃ»§·´À¬»øµ÷²éÀ¿ªá¡Ä»

------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field

List archives are viewable at:     
                http://www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages 
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu