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[SI-LIST] Re: Data bus skew

  • From: "mittalr@xxxxxxxxxx" <mittalr@xxxxxxxxxx>
  • To: nitinbhandari@xxxxxxxxxxx, si-list@xxxxxxxxxxxxx
  • Date: Tue, 9 Jul 2002 19:52:53 -0400 (EDT)

Certainly it seems like too much skew. I have Run 10G signals on Rogers 
material and have seen less than 15ps skew, because if it was anything more our 
circuit wouldn't have worked. Didn't do a TDR though.

One question:
how did you make sure input is not skewed. There are these components called 
verniers that we used to get the inputs fully matched and then tied them to the 
SMAs on our board.

Let me know if you want to find where to buy them from

 --- On Tue 07/09, nitin bhandari  wrote:
From: nitin bhandari [mailto: nitinbhandari@xxxxxxxxxxx]
To: si-list@xxxxxxxxxxxxx
Date: Tue 07/09
Subject: [SI-LIST] Data bus skew

> 
> 
> I am working on a source sync interface that allows for only 20ps skew 
> between various data bits in a bus. I built a test board (i'm glad i did)
> to 
> conduct a feasibility study. I am puzzled at the finding and am hoping
> that 
> someone can shed some light on it.
> 
> first, some background:
> 
> Dielectric is Nelco-13.
> Trace width is 4 mils.
> All traces are 8000 mils (+/- 50 mils) long.
> All traces are on the same layer and are referenced to the ground plane.
> All traces have SMA connectors on one end and a BGA chip on the other. For
> 
> the purpose of this study, the BGA is not stuffed on the board. So, all 
> traces end in an open circuit.
> All traces have equal number of vias.
> There is minimal switch-backs on all traces (with 5X spacing).
> 
> When i TDR the traces, i find that the skew between the traces can be as 
> much as 100ps. I am careful to de-skew the TDR channels and cables+SMA 
> connectors.
> 
> Has anyone seen this type of behavior on PCB traces. Can different
> portions 
> of the board have different velocity.
> 
> Can anyone suggest any experiments to debug this problem.
> 
> Thanks in advance,
> Nitin
> 
> 
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