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[SI-LIST] Re: Data bus skew

  • From: "Ibrahim Khan" <ikhan@xxxxxxxxxxxxxxxxxxx>
  • To: <nitinbhandari@xxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
  • Date: Tue, 9 Jul 2002 18:12:37 -0500
Nitin,
The 20ps skew is tough.  I have done a backplane with 1100 traces and
couple of test cards with BGA and SMA.  In all cases, I had only two
vias on a trace and my length was matched to 0.00000 mils. I saw 5ps
skew on Nelco-6000SI.
I think you may have too many vias and effectively 100 mils skew on
trace length.
What SMA connectors are you using and what is the anti-pad on the and
how well it is controlled in manufacturing.

Ibrahim Khan

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of nitin bhandari
Sent: Tuesday, July 09, 2002 5:39 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Data bus skew




I am working on a source sync interface that allows for only 20ps skew 
between various data bits in a bus. I built a test board (i'm glad i
did) to 
conduct a feasibility study. I am puzzled at the finding and am hoping
that 
someone can shed some light on it.

first, some background:

Dielectric is Nelco-13.
Trace width is 4 mils.
All traces are 8000 mils (+/- 50 mils) long.
All traces are on the same layer and are referenced to the ground plane.
All traces have SMA connectors on one end and a BGA chip on the other.
For 
the purpose of this study, the BGA is not stuffed on the board. So, all 
traces end in an open circuit.
All traces have equal number of vias.
There is minimal switch-backs on all traces (with 5X spacing).

When i TDR the traces, i find that the skew between the traces can be as

much as 100ps. I am careful to de-skew the TDR channels and cables+SMA 
connectors.

Has anyone seen this type of behavior on PCB traces. Can different
portions 
of the board have different velocity.

Can anyone suggest any experiments to debug this problem.

Thanks in advance,
Nitin


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