FreeLists / si-list / [SI-LIST] Re: power plane spacing

[Gonzo <degonzal@xxxxxxxxxxxxxxx>]

Hola people, 

This leads me to a couple of slightly different questions...perhaps already 
discussed or trivial so please forgive my ignorance...however I have seen many 
package designs where the associated GND is split, isolating the 2 adjacent 
power planes. I've also seen many cases where the GND plane is common for I/O 
power & core power in the package/substrate but is then isolated on the 
silicon. It is not intuitive to me why isolating GND planes is effective or 
recommended - particularly in the latter case where the I/O noise will not 
track across the level-shifter to the core logic.  

Sorry for the slight tangent but this mental splinter has been pestering me, 
and this seemed like a good foray.

Regards,
Dean  

-----Original Message-----
From:   Ritchey Lee [SMTP:leeritchey@xxxxxxxxxxxxx]
Sent:   Wednesday, July 11, 2001 2:50 PM
To:     si-list@xxxxxxxxxxxxx
Subject:        [SI-LIST] Re: power plane spacing


The small spacing has nothing to do with EMI.  It has to do with creating a
large value, high performance capacitor to supply switching currents.

Lee

DORIN OPREA wrote:

> Hi everyone,
>
> In high speed design we often use the split planes on a power layer. The
> spacing between the digital planes is correlated with the distance
> between the power layer to the ground layer. In general we have 50 mil
> spacing. It just happen to run into a different opinion which recommends
> a very small spacing due to the slot antenna effect (the gap between the
> planes) that allows the eddy currents to radiate. A small spacing may
> couple noise into the low power supply (1.5V or 1.8V).
> How critical is this radiation effect versus noise coupling between the
> two power distribution systems ?
> What is the practice out there ?
>
> Thanks very much for you guys always being there,
> Dorin
>
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